Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-12-22
2011-10-04
Thomas, Shane M (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711SE12057
Reexamination Certificate
active
08032711
ABSTRACT:
Embodiments of the invention are generally directed to systems, methods, and apparatuses for prefetching from a dynamic random access memory (DRAM) to a static random access memory (SRAM). In some embodiments, prefetch logic receives a prefetch hint associated with a load instruction. The prefetch logic may transfer two or more cache lines from an open page in the DRAM to the SRAM based, at least in part, on the prefetch hint.
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Annavaram Murali M.
Black Bryan
Devale John P.
McCauley Donald W.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Schnee Hal
Thomas Shane M
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