Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-04-18
2006-04-18
Sparks, Donald (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S213000, C712S205000, C712S207000
Reexamination Certificate
active
07032076
ABSTRACT:
A method and apparatus to detect and filter out redundant cache line addresses in a prefetch input queue, and to adjust the detector window size dynamically according to the number of detector entries in the queue for the cache-to-memory controller bus. Detectors correspond to cache line addresses that may represent cache misses in various levels of cache memory.
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Rohillah Anwar Q.
Sprangle Eric A.
Bacon Shireen I.
Intel Corporation
Sparks Donald
Truong Bao Q.
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