Prefetch processing apparatus, prefetch processing method,...

Details Prefetch processing apparatus, prefetch processing method,... Prefetch processing apparatus, prefetch processing method,...

2011-08-23

2011-08-23

Rojas, Midys (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S118000, C711S213000, C711S204000, C712S205000, C712S206000, C712S207000

Reexamination Certificate

active

08006041

ABSTRACT:
A prefetch processing apparatus includes a central-processing-unit monitor unit that monitors processing states of the central processing unit in association with time elapsed from start time of executing a program. A cache-miss-data address obtaining unit obtains cache-miss-data addresses in association with the time elapsed from the start time of executing the program, and a cycle determining unit determines a cycle of time required for executing the program. An identifying unit identifies a prefetch position in a cycle in which a prefetch-target address is to be prefetched by associating the cycle determined by the cycle determining unit with the cache-miss data addresses obtained by the cache-miss-data address obtaining unit. The prefetch-target address is an address of data on which prefetch processing is to be performed.

REFERENCES:
patent: 2004/0193807 (2004-09-01), Mogi et al.
patent: 2004/0268085 (2004-12-01), Hara et al.
patent: 2005/0210201 (2005-09-01), So et al.
patent: A 2004-295458 (2004-10-01), None
patent: A 2005-18553 (2005-01-01), None

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