Prefetch miss indicator for cache coherence directory misses...

Details Prefetch miss indicator for cache coherence directory misses... Prefetch miss indicator for cache coherence directory misses...

2008-07-01

2008-07-01

Portka, Gary J (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S137000, C711S146000

Reexamination Certificate

active

07395375

ABSTRACT:
A system, method and article of manufacture for reducing latencies associated with cache coherence directory misses on external caches in a shared distributed memory data processing system. A cache coherence directory is evaluated for possible prefetching of a directory entry into a directory cache. A prefetch miss indicator is set if the prefetch evaluation results in a directory miss. The prefetch miss indicator is consulted during subsequent processing of a memory block request corresponding to the directory entry. An accelerated snoop response action is taken if the prefetch miss indicator is set. The latency of a second lookup into the cache coherence directory, which would otherwise be required, is thereby avoided.

REFERENCES:
patent: 5715425 (1998-02-01), Goldman et al.
patent: 5835947 (1998-11-01), Cherabuddi
patent: 5854911 (1998-12-01), Watkins
patent: 5864671 (1999-01-01), Hagersten et al.
patent: 6012134 (2000-01-01), McInerney et al.
patent: 6243794 (2001-06-01), Casamatta
patent: 6272622 (2001-08-01), Han et al.
patent: 6321301 (2001-11-01), Lin et al.
patent: 7038972 (2006-05-01), Seo et al.
patent: 2002/0002659 (2002-01-01), Michael et al.
patent: 2003/0152076 (2003-08-01), Lee et al.
patent: 2003/0191866 (2003-10-01), Wolrich et al.
patent: 2004/0049640 (2004-03-01), So et al.
patent: 2004/0148473 (2004-07-01), Hughes et al.
patent: 2005/0210199 (2005-09-01), Dimpsey et al.
patent: 2005/0289551 (2005-12-01), Wojtkiewicz et al.
patent: 2006/0010339 (2006-01-01), Klein
A. Billingsly et al., “Memory Latency Reduction Using An Address Prediction Buffer”, IEEE Computer Society Press (1992), pp. 78-82.
J. D. Collins et al., “Runtime Identification Of Cache Conflict Misses: The Adaptive Miss Buffer”, ACM Transactions on Computer Systems, vol. 19, No. 4 (Nov. 2001), pp. 413-439.
Wei Fen Lin et al., “Designing A Modern Memory Hierarchy With Hardware Prefetching”, IEEE Transactions on Computers, vol. 50, No. 11 (Nov. 2001), pp. 1202-1218.

Affiliated with

Also associated with

Rating

Prefetch miss indicator for cache coherence directory misses... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Prefetch miss indicator for cache coherence directory misses..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Prefetch miss indicator for cache coherence directory misses... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2751144