Prefetch management for DMA read transactions depending upon pas

Details Prefetch management for DMA read transactions depending upon pas Prefetch management for DMA read transactions depending upon pas

1997-11-03

2000-01-04

Lee, Thomas C.

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

710 26, 710 52, 709 2, 711213, 711221, 711171, G06F 1208, G06F 1300

Patent

active

060121068

ABSTRACT:
A memory controller for optimizing direct memory access (DMA) read transactions wherein a number of cache lines are prefetched from a main memory as specified in a prefetch length field stored in a page table. When all prefetch data has been fetched, the memory controller waits to determine whether the initiator of the DMA read transaction will request additional data. If additional data is needed, additional cache lines are fetched. Once the initiator terminates the DMA read transaction, the prefetch length field for a selected page other entry in the table is updated to reflect the actual DMA read transaction length. As a result, an optimum number of cache lines are always prefetched thereby reducing the number of wait states required.

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"DECchip 21071 and DECchip 21072 Core Logic Chipsets," Mar. 1995.

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