Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-05-17
2005-05-17
Nguyen, Hiep T. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
Reexamination Certificate
active
06895475
ABSTRACT:
Methods and apparatus are provided for supplying data to a processor in a digital processing system. The method includes holding data required by the processor in a cache memory, supplying data from the cache memory to the processor in response to processor requests, performing a cache line fill operation in response to a chache miss, supplying data from a prefetch buffer to the cache memory in response to the cache line fill operation, and speculatively loading data from a lower level memory to the prefetch buffer in response to the cache line fill operation.
REFERENCES:
patent: 5317718 (1994-05-01), Jouppi
patent: 5420994 (1995-05-01), King et al.
patent: 5737750 (1998-04-01), Kumar et al.
patent: 5822790 (1998-10-01), Mehrotra
patent: 5835929 (1998-11-01), Gaskins et al.
patent: 5854911 (1998-12-01), Watkins
patent: 5860096 (1999-01-01), Undy et al.
patent: 5860111 (1999-01-01), Martinez et al.
patent: 5907860 (1999-05-01), Garibay et al.
patent: 6237074 (2001-05-01), Phillips et al.
patent: 20030236949 (2003-12-01), Henry et al.
Allen Michael S.
Volpe Thomas A.
Analog Devices Inc.
Nguyen Hiep T.
Wolf Greenfield & Sacks P.C.
LandOfFree
Prefetch buffer method and apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Prefetch buffer method and apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Prefetch buffer method and apparatus will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3386604