Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-05-13
1998-12-01
Lall, Parshotam S.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
395389, 711125, G06F 930
Patent
active
058451013
ABSTRACT:
A microprocessor is configured to speculatively fetch cache lines of instruction bytes prior to actually detecting a cache miss for the cache lines of instruction bytes. The bytes transferred from an external main memory subsystem are stored into one of several prefetch buffers. Subsequently, instruction fetches may be detected which hit the prefetch buffers. Furthermore, predecode data may be generated for the instruction bytes stored in the prefetch buffers. When a fetch hit in the prefetch buffers is detected, predecode data may be available for the instructions being fetched. The prefetch buffers may each comprise an address prefetch buffer included within an external interface unit and an instruction data prefetch buffer included within a prefetch/predecode unit. The external interface unit maintains the addresses of cache lines assigned to the prefetch buffers in the address prefetch buffers. Both the linear address and the physical address of each cache line is maintained. The prefetch/predecode unit receives instruction bytes directly from the external interface and stores the instruction bytes in the corresponding instruction data prefetch buffer.
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Gavin Matt T.
Johnson William M.
Pedneau Mike
Tran Thang M.
Advanced Micro Devices , Inc.
Coulter Kenneth R.
Kivlin B. Noel
Lall Parshotam S.
Merkel Lawrence J.
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