Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2000-11-28
2002-02-05
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S190000, C365S194000, C365S233100
Reexamination Certificate
active
06345007
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a prefetch and restore method and apparatus of a semiconductor memory device; particularly to a method and apparatus for, in a restore operation, driving a bit line sense amplifier after write data on a pair of global data bus lines is delivered to a pair of bit lines, so as to reduce a size of a driver used to invert a logic value of data sensed by the bit line sense amplifier when logic values of cell data and the write data are opposite in a restore operation and also decrease a power consumption and a noise.
BACKGROUND OF THE INVENTION
In general, when a weak data signal stored in a cell of a memory cell array is provided onto a pair of bit lines BL and /BL, a bit line sense amplifier detects the weak data signal and amplifies the detected data signal into a power voltage Vcc or a ground voltage Vss according to a logic value of the detected data signal.
Hereinafter, there will be explained a prefetch (or read) and restore (or write) operation in such memory devices as a dynamic random access memory (DRAM), synchronous DRAM and DRAMs (CDRAM, EDRAM, VCM, and the like) employing a memory buffer therein.
First of all, in the read (or prefetch) operation, the data stored in the memory cell is coupled to a pair of transfer bus lines via the bit line sense amplifier and then temporarily stored in a channel buffer. The temporarily stored data is outputted to the outside of the memory device via a data output buffer and an output pad.
In the write (or restore) operation, the write data inputted through an input pad is temporarily stored in the channel buffer via a data input buffer and then stored in the memory cell through the pair of data bus lines and the pair of bit lines.
There will be explained in detail the read or prefetch operation reading out cell data stored in a memory cell.
If a row address is inputted to the inside of the memory device, a word line corresponding to the row address is activated and a corresponding cell data is retrieved onto a pair of bit lines BL and /BL by a charge distribution. Then, if control signals RTO and SB are enabled to drive a bit line sense amplifier, the bit line sense amplifier amplifies a weak data signal on the pair of bit lines BL and /BL into the power voltage Vcc or the ground voltage Vss according to a logic value of the data signal. The time required from the inputting of the row address to the sensing of the data signal is called as a row active time tRCD.
After the row address is inputted, if a column address is inputted, a pair of bit lines BL and /BL selected by the column address are connected to a pair of global data bus lines GDB and /GDB and, hence, the data on the pair of bit lines BL and /BL are transferred onto the pair of global data bus lines GDB and /GDB.
The data on the pair of global data bus lines are amplified by the data line sense amplifier and then outputted to the outside of the memory device via a corresponding data output buffer.
There will be explained in detail the write or restore operation writing data onto a memory cell.
If a row address is inputted to the inside of the memory device, a word line corresponding to the row address is activated and a corresponding cell data is fed onto a pair of bit lines BL and /BL by the charge distribution. Then, if control signals RTO and SB are enabled to drive a bit line sense amplifier, the bit line sense amplifier amplifies the weak data signal on the pair of bit lines BL and /BL into the power voltage Vcc or the ground voltage Vss according to a logic value of the data signal. The time required for the above process is referred to as the row active time tRCD.
After then, if the pair of bit lines BL and /BL selected by the column address are connected to a corresponding pair of global data bus lines GDB and /GDB, write data is delivered onto the pair of global data bus lines GDB and /GDB in response to an operation of a write driver. At this time, since the pair of global data bus lines and the pair of bit lines are connected to each other, the write data on the pair of global data bus lines are transferred onto the pair of bit lines. Accordingly, the write data on the pair of bit lines are stored in the memory cell.
Referring to
FIG. 1
, there is illustrated a schematic diagram of explaining a structure of a virtual channel memory (VCM).
As described in
FIG. 1
, the VCM comprises a multiplicity of cell array units
10
<
0
> to
10
<N> each of which includes a plurality of memory cells; pairs of bit lines BL and BLB for connecting the memory cells with bit line sense amplifying units
20
<
0
> to
20
<N>; the bit line sense amplifying units
20
<
0
> to
20
<N> for detecting and amplifying the data on the pairs of bit lines BL and BLB; pairs of transfer bus lines TB<
0
> to TB<N> and TBB<
0
> to TBB<N> for connecting the bit line sense amplifying units
20
<
0
> to
20
<N> to a channel buffering unit
30
; transfer transistors N
1
and N
2
, and N
3
and N
4
for switching, in response to a control signal TB_CTRL, data between the pairs of bit lines BL and BLB and the respective pairs of transfer bus lines TB<
0
> to TB<N> and TBB<
0
> to TBB<N>; the channel buffering unit
30
for storing the data provided through the pairs of transfer bus lines TB<
0
> to TB<N> and TBB<
0
> to TBB<N>, or storing data provided from a read sense amplifier/write driver
40
; the read sense amplifier/write driver
40
for accessing data from the channel buffering unit
30
or delivering data to the channel buffering unit
30
; and an input/output (DQ) buffer/pad
50
for buffering data provided from the read sense amplifier
40
and outputting the data through an output pad, and buffering write data inputted through an input pad and transferring the write data to the write driver
40
.
In the prefetch (or read) operation of the above VCM, if a certain word line is activated along with a row path generated by a prefetch instruction, data stored in all of cells connected to the certain word line are coupled onto their respective pairs of bit lines BL and BLB. Then, if the sense amplifier driving signals RTO and SB are enabled in response to a control signal SG, all of bit line sense amplifying units
20
<
0
> to
20
<N> corresponding to the pairs of bit lines BL and BLB are activated and the data on the pairs of bit lines BL and BLB are sensed into the power voltage Vcc or the ground voltage Vss.
The sensed data on the pairs of bit lines BL and BLB are temporarily stored in the channel buffering unit
30
via the transfer bus lines TB<
0
> to TB<N> and TBB<
0
> to TBB<N> and then amplified by the data bus line read sense amplifier
40
to thereby being outputted to the outside of the memory device through the DQ buffer/pad
50
.
On the other hand, in the restore (or write) operation, write data are temporarily stored in the channel buffering unit
30
after being inputted via the input pad, the input buffer and the write driver in response to a write instruction. In order to store the temporarily stored data in the memory cells, a word line corresponding to the row path is actuated and, thereafter, the data stored in the memory cells are provided onto the pairs of bit lines BL and BLB by the charge distribution.
Referring to
FIG. 2
, there is shown a schematic diagram of explaining a process for generating conventional sense amplifier driving signals RTO and SB.
First of all, if a /RAS signal is enabled, a word line corresponding to an inputted row address is activated and then a sense amplifier driving signal generating circuit
22
is activated in response to a control signal SG to thereby produce the bit line sense amplifier driving signals RTO and SB.
Referring to
FIG. 3
, there is described a timing diagram of showing an activating order of a transfer bus line control signal TB_CTRL and sense amplifier driving signals RTO and SB in a prefetch operation.
As shown in
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Hyundai Electronics Industries Co,. Ltd.
Nguyen Tan T.
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