Preemptive write back controller

Details Preemptive write back controller Preemptive write back controller

2001-09-14

2008-12-30

Shah, Sanjiv (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S118000, C711S128000, C711S133000, C711S135000, C711S137000, C711S141000, C711S142000, C711S160000

Reexamination Certificate

active

07472230

ABSTRACT:
A preemptive write back controller is described. The present invention is well suited for a cache, main memory, or other temporarily private data storage that implements a write back strategy. The preemptive write back controller includes a list of the lines, pages, words, memory locations, or sets of memory locations potentially requiring a write back (i.e., those which previously experienced a write operation into them) in a write back cache, write back main memory, or other write back temporarily private data storage. Thus, the preemptive write back controller can initiate or force a preemptive cleaning of these lines, pages, words, memory locations, or sets of memory locations.

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Marcelo Cintra, et al., “Architectural Support for Scalable Speculative Parellelization in Shared-Memory Multiprocessors”, May 2000.

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