Preemptive packet flow controller

Details Preemptive packet flow controller Preemptive packet flow controller

2011-01-11

2011-01-11

Hafiz, Tariq R. (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Data transfer specifying

C710S001000, C710S006000, C710S020000, C710S035000, C710S040000, C710S059000, C370S389000, C370S392000, C370S396000, C370S410000, C370S412000, C370S414000, C370S465000, C370S473000

Reexamination Certificate

active

07870311

ABSTRACT:
Described is a system to control a flow of packets to and from an electronic processor which includes a packet processor engine programmed to interpret the packets from a packet memory, and to perform switching between packet chains in response to events, a working chain pointer register of the packet processor engine, programmed to indicate progress in executing an active buffer chain, prioritized pointer storage registers of the packet processor engine, each of the registers being programmed to point to one of the active buffer chains, a control register of the packet processor engine having chain start bits and chain protect bits, the chain start bits identifying the chains that have been started and wsa status register of the packet processor engine, having a chain actives group identifying the chain that is currently running, a chain matches group, a chain stops group identifying the chains that have been stopped and a timer expirations group.

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