Predriver logic circuit

Electronic digital logic circuitry – Interface – Current driving

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Details

326 83, 326 58, 326 27, 326 17, H03K 190175, H03K 19094

Patent

active

060436824

ABSTRACT:
A buffer for enabling a signal to be applied to a bus. The buffer includes a first transistor coupled to a bus and a voltage supply. The logic buffer includes a first logic circuit which has an input coupled to receive a data signal and adapted to charge a terminal of the transistor at a first rate in response to a transition in the data signal. A second logic circuit charges the terminal at a faster rate during an initial transition period, until a first preselected condition is met. The buffer also includes a third logic circuit to charge the terminal at a second faster rate during a final transition period, after a second preselected condition is met. A method for controlling a voltage level of a signal applied to a terminal of a transistor includes charging the terminal at a fast rate until a first preselected condition is met. The terminal is then charged at a slower rate, until a second preselected condition is met, at which time the terminal is charged at a second fast rate, which is also greater than the slower rate.

REFERENCES:
patent: 5043604 (1991-08-01), Komaki
patent: 5055713 (1991-10-01), Watanabe et al.
patent: 5424653 (1995-06-01), Folmsbee et al.
patent: 5684410 (1997-11-01), Guo
patent: 5850159 (1998-12-01), Chow et al.
patent: 5877638 (1999-03-01), Lin

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