Predictive status flag generation in a first-in first-out (FIFO)

Details Predictive status flag generation in a first-in first-out (FIFO) Predictive status flag generation in a first-in first-out (FIFO)

1994-06-29

1996-04-09

Nguyen, Viet Q.

Static information storage and retrieval

Read/write circuit

Serial read/write

36518907, 36523001, 36518901, 365233, 3652335, 365236, G11C 700, G11C 800

Patent

active

055068090

ABSTRACT:
Method and apparatus are described for generating more accurate and timely FIFO status flags. Preferably, the asynchronous FIFO read and write pointers are conventionally compared with one another and the output of such comparison is glitch-suppressed. During such operation in accordance with the invented method and apparatus, prediction signals are used to precondition the status flag output latches so that they will provide the earliest possible accurate status reflecting asynchronous read and write clock activity. If a boundary condition is present--e.g. depending upon the next read or write clock activity, the FIFO's half full status flag may change where such change is impossible to predict because it is unknowable whether the next operation will be a read or a write or both--then an asynchronous state machine takes over from the prediction flag logic to ensure accurate and early preconditioning of the status flags' output latches. When no such boundary condition is present, the state machine is dormant and the prediction logic is active.

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