Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-05-06
1998-09-22
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
G06F 1328, G06F 1208
Patent
active
058130365
ABSTRACT:
When a PCI-bus controller receives a request from a PCI-bus master to transfer data with an address in secondary memory, the controller performs an initial inquire cycle and withholds TRDY# to the PCI-bus master until any write-back cycle completes. The controller then allows the burst access to take place between secondary memory and the PCI-bus master, and simultaneously and predictively, performs an inquire cycle of the L1 cache for the next cache line. In this manner, if the PCI burst continues past the cache line boundary, the new inquire cycle will already have taken place, or will already be in progress, thereby allowing the burst to proceed with, at most, a short delay. Predictive snoop cycles are not performed if the first transfer of a PCI-bus master access would be the last transfer before a cache line boundary is reached.
REFERENCES:
patent: 5341427 (1994-08-01), Hardy et al.
patent: 5535363 (1996-07-01), Prince
patent: 5630094 (1997-05-01), Hayek et al.
Intel, "Pentium Family User's Manual--vol. 2:82496/82497 Cache Controller and 82491/82492 Cache SRAM Data Book"; pp. 3-18, 3-19, & 5-95, 1994.
Ghosh Subir
Tung Hsu-Tien
Chan Eddie P.
Ellis Kevin L.
OPTi Inc.
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