Predictive read cache memories for reducing primary cache miss l

Details Predictive read cache memories for reducing primary cache miss l Predictive read cache memories for reducing primary cache miss l

1997-11-04

2000-04-04

Bragdon, Reginald G.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711122, 711 3, G06F 1208

Patent

active

060473592

ABSTRACT:
A predictive read cache reduces primary cache miss latency in a microprocessor system that includes a microprocessor, a main memory and a primary cache memory connected between the main memory and the microprocessor via an instruction address bus, a data address bus and a data bus. The predictive read cache tracks the pattern of data read addresses that cause misses in the primary cache and associates the pattern with the specific instruction that generates the pattern of miss addresses. When a pattern has been determined, the address where the next cache data read miss will occur is predicted and sent to memory at a time when the memory is not busy with other transactions. The data at the predicted miss address is then fetched and stored in the predictive read cache. The next time a data read miss occurs in the primary cache, if the miss address matches one of the predicted miss addresses stored in the cache, then the required data is immediately sent to the primary cache from the predictive cache, rather than having to be read out of the much slower main memory.

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Fouts, Douglas J. and Arthur B. Billingsley, "Predictive Read Caches: An ernative to On-Chip Second-Level Cache Memories", Journal of Microelectronic Systems Integration, vol. 2, No. 2, pp. 109-121, Jun. 1994 .

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