Predictive mechanism for ASB slave responses

Details Predictive mechanism for ASB slave responses Predictive mechanism for ASB slave responses

1999-11-04

2003-06-10

Dharia, Rupal (Department: 2781)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S104000, C710S105000, C710S106000

Reexamination Certificate

active

06578098

ABSTRACT:

FIELD OF THE INVENTION
The present invention is related to a computer bus system. More specifically, the present invention is related to ASB (advanced system bus) slave responses.
BACKGROUND
ASB Bus:
As a microprocessor implementing RISC (reduced instruction set computer) architecture, an ARM (advanced RISC machine) microprocessor is not designed to work within a multiple masters computer system. Yet, by having multiple masters and multiple slaves within a computer system, the computer system gains more versatility in the types of functionalities that can be performed. Thus, in order for an ARM microprocessor to reap various benefits (e.g., functional versatility) associated with having a multiple masters/multiple slaves computer system, the ASB bus was introduced. Typically within the ASB system, multiple masters and slaves are coupled to the ASB bus. The ASB bus allows and supports an ARM microprocessor to function as the part of a multiple masters/multiple slave environment. In particular, the ASB bus is a widely used microprocessor system bus for computer systems based on the ARM family of microprocessors. Furthermore, the nomenclature and concepts relating to the ASB system are explained in detail in “Advanced Microcontroller Bus Architecture Specification” published in 1997 by Advanced RISC Machines Ltd. The following discussion will also adapt the nomenclature of this reference.
Referring now to
FIG. 1
, a generic ASB system
100
is depicted as having: an ASB bus
110
; two ASB masters A and B (e.g., ARM Processor, PCI (peripheral component interconnect) to ASB Masters etc.); two ASB slave devices X and Y (e.g., memory controllers, slave devices); an ASB decoder
105
(centralized decoder that selects a slave by asserting a device select signal, Dsel); and an ASB Arbiter
107
(arbitrates the bus among multiple masters). Furthermore, a PCI bus
120
is coupled to ASB bus
110
via slave Y. PCI bus
120
is coupled to devices such as PCI devices P and Q that run at slower speed than ASB system
100
.
ASB decoder
105
performs the decoding of the data transfer addresses, then selects slaves according to the decoded addresses. ASB arbiter
107
ensures that only one bus master at a time is allowed to initiate data transfers. Masters A and B can initiate a read or a write data transfer. Only one master is allowed by arbiter
107
to access ASB bus
10
at one time. Slaves X and Y respond to a read or a write data transfer. Slaves such as X and Y signal back to the active master the success, failure or extension of the data transfer. Furthermore, when a data transfer is intended for a peripheral device such as PCI device Q, the slower speed of PCI device Q causes latency in slave Y's responses to the data transfer. For this reason, slave Y can be called a lower “latency” slave of ASB system
100
.
Slave Responses within an ASB System:
Referring still to
FIG. 1
, a multiple masters/slaves system bus such as ASB bus
110
necessitates coordination of bus access among the masters and the slaves. Unfortunately, this bus access coordination in turn gives rise to many issues that, if unresolved, can lead to a congested and an inefficient bus architecture. One such issue is ensuring synchronous slave responses with respect to a data transfer. Specifically, in order for ASB bus
110
to function at high clock speed, slave responses need to be driven synchronously onto ASB bus
110
. But certain slaves such as slave Y cannot easily respond synchronously because these slaves have slave response latency. Typically, slave response latency comes from slaves (e.g., slave Y) that are coupled to peripheral devices (e.g., PCI device Q) having slower processing speed compared to ASB bus
110
.
In particular, certain slaves such as slave Y can constitute intermediary stations between a master such as the ARM microprocessor and a slower peripheral device such as PCI device Q. In order for the ARM microprocessor to communicate with slower peripherals without impacting the system performance, an intermediate “agent” such as slave Y is used as a slave of the ASB bus. This “agent” slave, traditionally called the “bridge” facilitates the communication between the ARM microprocessor (via the ASB bus) and the slower peripherals. Moreover, the slower peripherals can communicate with the ARM processor through such a bridge via a standard interface such as VPB, PCI, APB or their own customary interfaces. Common examples of these peripherals include devices like IDE (integrated drive electronics) disk controllers, UART's (universal asynchronous receiver transmitter) etc., which are slow compared to the microprocessor system bus such as ASB bus
110
.
As an example, referring still to
FIG. 1
, when master A accesses a slow device, such as PCI device Q that is coupled to slave Y, time is needed to compensate for the difference in speeds between master A and the slow PCI device Q. That is, when master A attempts to access the slow PCI device Q, this PCI device Q might not be able to respond to master A immediately. Also, the speed difference between ASB bus
110
and PCI bus
120
creates uncertainty in the timing of slave responses for slave Y. As latency is created at slave Y (hence “latency” slave), driving slave responses synchronously becomes less straightforward. Also, traditionally, the slave devices on ASB bus
110
do not synchronize the incoming signals from a master. Thus, various prior art approaches were implemented to achieve synchronous slave responses in view of these considerations.
Prior Art Implementations:
In order to synchronize slave responses in view of these conditions, the prior art slave devices either a) drive the outputs combinatorially or b) insert wait states. The former method is a bad design practice because it can cause glitches in the timing of ASB bus
110
. Moreover, this former method is slow to execute; thus, it limits the speed of operation of the bus. The latter method of inserting wait states affects the system performance and bus throughput. Specifically, in the prior art ASB systems, the ASB slave devices rely on a device select signal “Dsel” (driving by address decoder
105
) to make decisions for that clock cycle in which they are addressed. Dsel is a combinatorial decode of 32 address lines generated by the address decoder and hence is a late arriving signal. Typical timing numbers for a 100 MHz ASB bus slave is shown in FIG.
2
.
Referring now to
FIG. 2
, Dsel
251
is driven on the rising edge of Bclk
250
in cell
203
and can take as many as 4 nano seconds to be valid (see TisDsel
222
, the input setup time for Dsel). The slave device sampling this Dsel
251
has to use this Dsel signal to drive slave responses. These slave responses are comprised of Bwait
255
, Blast
257
and Berror
259
signals that are sampled in the next rising edge of Bclk
250
as shown in FIG.
2
. This means that the raw Dsel
251
signal needs to be used as such to make a decision to drive the Bwait
255
, Blast
257
and Berror
259
signals even while inserting wait states to achieve synchronous slave responses.
This prior art implementation of synchronous slave responses has at least the following drawbacks. First, use of raw Dsel
251
implies that there can be no high-speed ASB cycles without wait states. Second, registering Dsel
251
inplies that there needs to be at least one clock wait state which results in low performance of the ASB bus. Third, driving Bwait
255
, Blast
257
and Berror
259
based on raw Dsel
251
with some combinatorial logic to make the decisions implies that the ASB system can only run at a limited speed. Fourth, using the above implies that the outputs can glitch, hence providing a very dangerous scenario in terms of reliability. Fifth, use of combinatorial outputs makes timing analysis difficult. All these drawbacks can deleteriously affect the performance of the ASB bus. In all, the ASB bus performance relies on synchronous slave responses. Unfortunately, in the prior art implementations, driving slave responses synchronously

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