Predictive event scheduling in an iterative tran resolution...

Details Predictive event scheduling in an iterative tran resolution... Predictive event scheduling in an iterative tran resolution...

2007-07-31

2007-07-31

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

10957106

ABSTRACT:
A method and system for resolving circuit and network parameters. A circuit evaluation system includes a plurality of nodes and a plurality of resolution devices. Each node is connected to a resolution device via a bi-directional connection, and at least one node is configured to receive data from an input. Each enabling element is associated with a resolution device. Enabling elements that are associated with resolution devices that are connected to nodes that are configured to receive input data are activated, thereby enabling certain resolution devices. The enabled resolution devices are executed using data in the nodes that are connected to the enabled resolution devices. Iterations of executing resolution devices are performed until stable node values are determined.

REFERENCES:
patent: 6850999 (2005-02-01), Mak et al.
patent: 2002/0163889 (2002-11-01), Yemini et al.
Kaiser, D.R., et al., “Performance Optimizations in NC-Verilog”, Proceedings Cadence Technical Conference 1997, May 1997.
Cadence® NC-Verilog® Simulator Help, Product Version 5.1, User's Manual, Sep. 2003 (1000+ pages).

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