Predictive caching system and method based on memory access whic

Details Predictive caching system and method based on memory access whic Predictive caching system and method based on memory access whic

1997-11-25

1998-07-07

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711122, G06F 1212

Patent

active

057784361

ABSTRACT:
Predictive cache memory systems and methods are responsive to cache misses to prefetch a data block from main memory based upon the data block which last followed the memory address which caused the cache miss. In response to an access request to main memory for a first main memory data block, which is caused by a primary cache miss, a second main memory data block is identified which was accessed following a previous access request to the main memory for the first main memory data block. Once identified, the second memory data block is stored in a predictive cache if the second main memory data block is not already stored in the predictive cache. Thus, if the next main memory request is for the second main memory block, as was earlier predicted, the second main memory block is already in the predictive cache and may be accessed rapidly. The identification of data blocks for prefetching may be provided by a prediction table which stores therein identifications of a plurality of succeeding main memory data blocks, each of which was accessed following an access request to a corresponding one of a plurality of preceding main memory data blocks. The Prediction Table is updated if predictions are incorrect. The predictive cache may be implemented using on-chip SRAM cache which is integrated with a DRAM array so that transfers between the DRAM array and the predictive cache may occur at high speed using an internal buffer.

REFERENCES:
patent: 4807110 (1989-02-01), Pomerane et al.
patent: 4860199 (1989-08-01), Langendorf et al.
patent: 5148538 (1992-09-01), Celtruda et al.
patent: 5210845 (1993-05-01), Crawford et al.
patent: 5305389 (1994-04-01), Palmer
patent: 5418922 (1995-05-01), Liu
patent: 5499355 (1996-03-01), Krishnamohan et al.
patent: 5521878 (1996-05-01), Ohtani et al.
patent: 5530941 (1996-06-01), Weisser et al.
Lopriore, Line Fetch/Prefetch in a Stack Cache Memory, Microprocessors and Microsystems, vol. 17, No. 9, Nov. 1993, pp. 547-555.
Eickemeyer et al., A Load-Instruction Unit for Pipelined Processers, IBM J. Res. Develop., vol. 37, No. 4, Jul. 1993, pp. 547-564.
Nowicki, Masters Thesis: The Design and Implementation of a Read Prediction Buffer, Navel Postgraduate School, Monterey, California, 1992.
Palmer et al., Fido: A Cache that Learns to Fetch, Proceedings of the 17th International Conference on Very Large Data Bases, Sep. 1991, pp. 255-264.
Vitter et al., Optimal Prefetching Via Data Compression, Technical Report No. CS-91-46, Computer Science Department, Brown University, 1991.

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