Prediction of impact on post-repair yield resulting from...

Details Prediction of impact on post-repair yield resulting from... Prediction of impact on post-repair yield resulting from...

2006-08-31

2011-10-11

Gaffin, Jeffrey A (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S741000

Reexamination Certificate

active

08037379

ABSTRACT:
A method for predicting an impact on post-repair yield resulting from manufacturing process modification is described. The method includes receiving bit data representing locations of defective memory cells for a plurality of memory devices. The bit data is modified by removing a selected failure pattern type according to a modification scheme to generate modified bit data. Repairs are simulated on hypothetical memory devices corresponding to the modified bit data, generating a result indicating whether the hypothetical memory device is good or bad. A post-repair yield is then identified and a report is generated indicating the post-repair yield, the post-repair yield representing a number of the plurality of memory devices that would be functional after repair had the plurality of memory devices been manufactured without the selected failure pattern. A method to identify a process providing the best economic benefit is also described.

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