Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-07-31
2007-07-31
Whitmore, Stacy A. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
10770711
ABSTRACT:
A method for facilitating semiconductor wafer lot disposition includes providing detailed descriptive information of the semiconductor wafer layout and generating data concerning at least one defect in the semiconductor wafers at an intermediate processing stage. At least one layer model is generated from the information and data to disclose the effects of the defect upon at least one later layer of the semiconductor wafers. The layer model is utilized to determine the subsequent disposition of the wafer lot.
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Advanced Micro Devices , Inc.
Dimyan Magid Y.
Ishimaru Mikio
Whitmore Stacy A.
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