Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2001-10-09
2003-08-12
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S086000, C326S090000, C327S108000
Reexamination Certificate
active
06605958
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to high speed transmission of data and in particular to systems and methods of terminating transmission lines.
Use of high speed data lines is widely prevalent. Often transmission speeds are above 1 Gbps. At high data transmission speeds a data line behaves in some respects as a transmission line and transmission line effects can result in ringing and distortion of the transmitted signal. Transmission line effects can be minimized by placing a termination resistor of resistance equal to the characteristic impedance of the transmission line at the receiver end of the transmission line and thereby impedance match the transmission line and the termination resistor.
When the receiver is a semiconductor device, a number of difficulties in impedance matching the transmission line may arise. For example, a number of problems are presented by using a termination resistor external to the receiving semiconductor device. When external termination resistors are used, a separate resistor is generally required for each transmission line. These resistors increase the complexity of the PCB because they occupy valuable area on the circuit board. In addition, termination resistors mounted on a PCB are unable to prevent transmission line effects due to unterminated transmission line stubs between the resistors and a receiving semiconductor device.
Other problems are presented when transmission lines are terminated using on-chip resistors. Process variation in the manufacture of semiconductor devices can result in variations in resistor resistance of, for example, up to ±30%. This varying resistance value can result in improper termination values. Furthermore, once the internal termination resistor is included on-chip, changing the resistance becomes difficult.
SUMMARY OF THE INVENTION
The present invention provides a method and apparatus for providing precision on-chip termination of transmission lines. One embodiment of the invention includes a first reference resistor and an integrated circuit, which includes a resistor network and control circuitry. The configuration of the resistor network is capable of being controlled by the control circuitry such that the resistance of the resistor network is related to the resistance of the reference resistor.
A further embodiment includes a first reference resistor, an integrated circuit, which includes a resistor network and control circuitry and a transmission line connected to the integrated circuit. The resistor network provides a termination resistance across the transmission line and the configuration of the resistor network is capable of being controlled by the control circuitry such that the resistance of the resistor network is related to the resistance of the reference resistor. In a further embodiment of the invention, the integrated circuit also includes a reference resistor network and reference resistor network control circuitry. The configuration of the reference resistor network is capable of being controlled by the reference resistor control circuitry such that the resistance of the reference resistor network is related to the resistance of the reference resistor. The configuration of the resistor network is also capable of being controlled by the control circuitry such that the resistance of the resistor network is related to the resistance of the reference resistor network. In addition, the resistance of the external reference resistor is chosen so that the resistance of the resistor network is substantially the same as the characteristic impedance of the transmission line.
A further embodiment of the invention involves controlling the configuration of a termination resistor network on an integrated circuit such that the resistance of the termination resistor network is related to the resistance of a reference resistor located on the printed circuit board. A further embodiment of the invention also involves controlling the configuration of a reference resistor network on the integrated circuit such that the resistance of the reference resistor network is related to the resistance of a reference resistor located on the printed circuit board. In addition the termination reference resistor network is configured such that the resistance of the termination resistor network is related to the resistance of the reference resistor network. The configuring step causes the termination resistor network to have substantially the same configuration as the reference resistor network. A further embodiment involves the resistance of the reference resistor being chosen such that the resistance of the termination resistance network is substantially the same as the characteristic impedance of the transmission line.
REFERENCES:
patent: 5864584 (1999-01-01), Cao et al.
patent: 6046653 (2000-04-01), Yamada
patent: 6157206 (2000-12-01), Taylor et al.
patent: 6424169 (2002-07-01), Partow et al.
Bergman Dave
Hu Yaqi
McDonald Jim
Tan Kok-Lean
Tan Vibol
Tokar Michael
Vitesse Semiconductor Corporation
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