Precision jitter-free frequency synthesis

Details Precision jitter-free frequency synthesis Precision jitter-free frequency synthesis

2006-06-20

2006-06-20

Ghebretinsae, Temesghen (Department: 2637)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C327S147000, C327S156000, C708S271000

Reexamination Certificate

active

07065172

ABSTRACT:
An electronic system (10) includes a phase-locked loop (30) and a frequency synthesis circuit (20), for generating a jitter-free output clock (CLK1,CLK2) at a desired frequency. The phase-locked loop (30) includes a voltage-controlled oscillator (37) that produces a number (N) of equally spaced clock phases at a frequency (fVCO) that depends also upon a programmable feedback frequency divider (38) and a prescale divider (32). The frequency synthesis circuit (20) generates the output clock (CLK1,CLK2) at a frequency under the control of a frequency select word (FREQ) that indicates the number of clock phases between successive clock edges. A central processing unit (12), either itself or from a look-up table (13), generates a feedback divide integer (M) and the frequency select word (FREQ) according to a desired frequency (f), by way of a minimization of the frequency error. The frequency of the output clock (CLK1,CLK2) can be generated in a jitter-free manner, since only integer values are used in the frequency synthesis circuit (20), at relatively low frequency error.

REFERENCES:
patent: 6081164 (2000-06-01), Shigemori et al.
patent: 6329850 (2001-12-01), Mair et al.
patent: 6366174 (2002-04-01), Berry et al.
patent: 2001/0005408 (2001-06-01), Neukon
Xiu et al., “A ‘Flying-Adder’ Architecture of Frequency and Phase Synthesis with Scalability”,Trans.on VLSI Sys., vol. 10, No. 5 (IEEE, Oct. 2002), pp. 637-649.
Mair et al., “An Architecture of High-Performance Frequency and Phase Synthesis”,J. of Solid State Cir., vol. 35, No. 6 (IEEE, Jun. 2000), pp. 835-846.

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