Precision bypass clock for high speed testing of a data...

Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Multiple or variable intervals or frequencies

Reexamination Certificate

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C713S600000

Reexamination Certificate

active

07007188

ABSTRACT:
A system clock circuit that provides a high-speed reference clock signal for operating an integrated circuit. The system clock circuit comprises a frequency combiner circuit that receives a first external clock signal having a frequency F1 and a second external clock signal having frequency F2, where F2 is an integer multiple of F1. The second external clock signal is phase-shifted by P degrees with respect to the first external clock signal. The frequency combiner circuit generates from the first and second external clock signals a first output clock signal having an operating frequency that is the sum of F1 and F2. The system clock circuit also comprises a clock selection circuit that selectively applies the first output clock signal to the integrated circuit.

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patent: 6052811 (2000-04-01), Ahsuri
patent: 6385125 (2002-05-01), Ooishi et al.
patent: 6480045 (2002-11-01), Albean

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