Precise delay measurement through combinatorial logic

Details Precise delay measurement through combinatorial logic Precise delay measurement through combinatorial logic

2008-02-29

2010-10-05

Wachsman, Hal D (Department: 2857)

Data processing: measuring, calibrating, or testing

Testing system

Signal generation or waveform shaping

C702S117000, C702S118000, C702S079000, C326S016000

Reexamination Certificate

active

07809521

ABSTRACT:
A high resolution circuit and method for facilitating precise measurement of on-chip delays for FPGAs for reliability studies. The circuit embeds a pulse generator on an FPGA chip having one or more groups of LUTS (the “LUT delay chain”), also on-chip. The circuit also embeds a pulse width measurement circuit on-chip, and measures the duration of the generated pulse through the delay chain. The pulse width of the output pulse represents the delay through the delay chain without any I/O delay. The pulse width measurement circuit uses an additional asynchronous clock autonomous from the main clock and the FPGA propagation delay can be displayed on a hex display continuously for testing purposes.

REFERENCES:
patent: 5631596 (1997-05-01), Sporck et al.
patent: 5822228 (1998-10-01), Irrinki et al.
patent: 5923676 (1999-07-01), Sunter et al.
patent: 6075418 (2000-06-01), Kingsley et al.
patent: 6081473 (2000-06-01), Agrawal et al.
patent: 6466520 (2002-10-01), Speyer et al.
patent: 6538465 (2003-03-01), Demone
patent: 6983394 (2006-01-01), Morrison et al.
patent: 7256610 (2007-08-01), Balasubramanian et al.
patent: 2003/0098731 (2003-05-01), Tabatabaei et al.
patent: 2005/0149777 (2005-07-01), Yuan et al.
Mattia Ruffoni et al., “Direct Measures of Path Delays on Commercial FPGA Chips”, 6th IEE Workshop on. Proceedings volume Issue . 2002 pp. 157-159.
Santos A, CMOS delay locked and sub-nanosecond time-to-digital converter chip, IEEE Trans on Nuclear Science, vol. 43, pp. 1717-1719, Jun. 1996.
Abramovici M. and Stroud C. , “BIST-based delay-fault testing in FPGAs,” Journal of Electronic Testing, vol. 19, No. 5, pp. 549-558, Oct. 2003.
Premachandran R. et al.. Design-Specific Path Delay Testing in Lookup Table-based FPGAs, Transactions on Computer-Aided Design of Integrated Circuits . . . , vol. XX, No. Y (2005).
Chmelar E. “FPGA interconnect delay fault testing,” in IEEE Int. Test Conf., Charlotte, NC, Sep. 2003, pp. 1239-1247.
Tahoori M. and Miltra S., “Interconnect delay testing of designs on programmable logic devices,” in IEEE Int. Test Conf., Charlotte, NC, Oct. 2004.

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