Precharged bit decoder and sense amplifier with integrated latch

Details Precharged bit decoder and sense amplifier with integrated latch Precharged bit decoder and sense amplifier with integrated latch

1995-01-13

1996-09-03

Zarabian, A.

Static information storage and retrieval

Read/write circuit

Differential sensing

365203, G11C 1140

Patent

active

055530290

ABSTRACT:
A memory and sense amplifier with latched output included therein derives high speed and noise immunity with precharged logic circuits through the separation of sense amplifier enablement and resetting by use of the precharge operation. Inclusion of bit line decoders which are wholly or partially self-resetting and self-precharging in sense amplifier support circuitry allows high performance at extremely short memory operation cycle times. A multiplexor is included which is usable in operating cycles as well as test cycles of the memory and further, in combination with other elements of the memory and sense amplifier arrangement, enables the pipelining of plural memory operations in a single memory cycle.

REFERENCES:
patent: 4843264 (1989-06-01), Galbraith
patent: 5204560 (1993-04-01), Bredin
patent: 5228106 (1993-07-01), Ang
patent: 5343428 (1994-08-01), Pilo

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