Precharged adiabatic pipelined logic

Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates

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326 96, 326 98, H03K 19096

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active

056024975

ABSTRACT:
The present invention relates to an implementation of adiabatic circuitry using a pipeline structure which allows for simultaneous evaluation of cascaded functions, which does not require each logic function to be implemented in dual complimentary circuitry, which does not require reversible logic functions, which does not require the use of diodes to insure adiabatic current flow, and which can be implemented using MOS technology. A significant feature of the present invention relates to use of a six-phase clock cycle associated with six phases of circuit operation including, in order, a precharge phase, a precharge disable phase, an evaluate phase, a hold phase, a precharge enable phase and a guard phase. Another significant feature of the present invention relates to simultaneous evaluation of cascaded logic functions during a single phase of operation.

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patent: 5506519 (1996-04-01), Avery et al.
patent: 5521538 (1996-05-01), Dickinson
"Low Power Digital Systems Based on Adiabtic Switching Principles" Athas et al, IEEE Trans, on VLSI Systems, Dec. 1994, pp. 398-407.
"Adiabatic Computing with the 2N-2N2D Logic Family" Kramer et al, 1994 Symposium on VLSI Digest of Technical Papers, pp. 25-26.
"Design and Analysis of a Low-Power Energy-Recovery Adder" Athas et al 1995 pp. 66-69.
"Power Dissipation Measurements on Recovered Energy Logic" Hinman et al, 1994 Symposium on VLSI Circuits Digest of Tech, Papers, p. 1920.
"An Energy Efficient CMOS Line Driver Using Adiabiatic Switching", Athas et al, IEEE, 1994, pp. 196-199.
"A Framework for Practical Low Power Digital CMOS Systems Using Adiabatic Switching Principles," Athas et al, from Internet.

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