Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Patent
1995-12-20
1997-02-11
Hudspeth, David R.
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
326 96, 326 98, H03K 19096
Patent
active
056024975
ABSTRACT:
The present invention relates to an implementation of adiabatic circuitry using a pipeline structure which allows for simultaneous evaluation of cascaded functions, which does not require each logic function to be implemented in dual complimentary circuitry, which does not require reversible logic functions, which does not require the use of diodes to insure adiabatic current flow, and which can be implemented using MOS technology. A significant feature of the present invention relates to use of a six-phase clock cycle associated with six phases of circuit operation including, in order, a precharge phase, a precharge disable phase, an evaluate phase, a hold phase, a precharge enable phase and a guard phase. Another significant feature of the present invention relates to simultaneous evaluation of cascaded logic functions during a single phase of operation.
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