Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1997-08-13
2001-08-21
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C365S201000, C438S014000, C324S765010
Reexamination Certificate
active
06279141
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to DRAM (dynamic random access memory) modules, and more particularly, to a preburn-in DRAM module circuit board which is directly connectable to a burn-in oven for performing a burn-in process concurrently on a plurality of DRAM modules mounted thereon.
2. Description of Related Art
FIG. 1
shows a conventional DRAM module circuit board which is mounted with an array of DRAM modules
100
thereon. Each of these DRAM modules
100
can be cut apart from the circuit board to function as a single memory unit. This conventional DRAM module circuit board is not provided with a burn-in circuit, so that the burn-in process for the DRAM modules
100
on the circuit board is performed for the DRAM modules
100
after they are cut apart from the circuit board.
Most conventional DRAM modules are manufactured by the following procedural steps: (1) wafer sorting, which is also called chip-probe (CP) testing; (2) IC package assembly; (3) final testing-1; (4) burn-in; (5) final testing-
2
; (6) module assembly; (7) module testing; and (
8
) shipping.
Some low-end DRAM modules are manufactured by a simplified procedure which includes the following steps: (1) wafer sorting (CP testing), (2) IC package assembly or chip-on-board, (3) module assembly, (4) module system burn-in, (5) module testing, and (6) shipping.
Conventional manufacturing processes for DRAM modules have some drawbacks. First, the procedure is quite complex and time-consuming to complete. Second, the burn-in and module warm-up should be separately carried out, each process requiring one or two days to complete, which is quite inconvenient and time-consuming. Third, the circuit board used for the burn-in process and that used for constructing the DRAM modules are separate ones, which means that the DRAM modules should be cut apart from the DRAM module circuit board and then mounted on a burn-in circuit board to undergo the burn-in process. The work involved is thus quite laborious and cost-ineffective. Fourth, the module warm-up process is applicable to one module only at a time, which is quite inefficient. Fifth, in the module warm-up process, the voltage and current can not be s suitably controlled, which can cause degradation to the IC quality and reliability.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a preburn-in DRAM module circuit board whose architecture represents a solution to the above-mentioned drawbacks of the prior art. In particular, the preburn-in DRAM module circuit board of the invention allows a plurality of DRAM modules to be constructed directly thereon, and which can be directly connected to a large burn-in oven so as to perform a burn-in process concurrently on the DRAM modules mounted thereon to check for any defected IC chips that are to be reworked.
It is another objective of the present invention to provide a structure for the DRAM modules (hereinafter referred to as preburn-in DRAM module) that are to be constructed on the preburn-in DRAM module circuit board, which includes a burn-in circuit and a module circuit that allow the preburn-in DRAM modules to undergo the burn-in process when they are still mounted on the same printed circuit board (PCB)
In accordance with the foregoing and other objectives of the present invention, a preburn-in DRAM module circuit board and a structure for the associated DRAM modules are provided.
The preburn-in DRAM module circuit board of the invention is directly connectable to a burn-in oven for performing a burn-in process concurrently on a plurality of preburn-in DRAM modules mounted thereon. This preburn-in DRAM module circuit board is configured to provide at least one test area which includes:
(a) a plurality of serially connected preburn-in DRAM modules; and
(b) a burn-in signal buffer/distributor, coupled to receive a burn-in signal from said burn-in oven, for transferring said burn-in signal to each of said plurality of preburn-in DRAM modules so as to perform a burn-in process concurrently on said plurality of preburn-in DRAM modules.
In a first preferred embodiment, each of the plurality of the above-mentioned preburn-in DRAM modules includes:
(a) a plurality of DRAM chips; and
(b) a printed circuit board partitioned into a module region and a removable dummy region, said printed circuit board being a double-layer structure including:
(i) a module circuit layer on which said DRAM chips are mounted in said module region;
(ii) a burn-in circuit layer in which a burn-in circuit is arranged; and
(iii) a ground plane formed between said module circuit layer and said burn-in circuit layer
During a burn-in process, a burn-in signal is received and directed by said burn-in circuit in said burn-in circuit layer to be transferred through said dummy region of said printed circuit board to said module circuit layer and subsequently into said DRAM chips.
In another preferred embodiment, each of the plurality of preburn-in DRAM modules includes:
(a) a first array of DRAM chips;
(b) a second array of DRAM chips; and
(c) a printed circuit board partitioned into a module region and a removable dummy region, said printed circuit board being a fourth-layer structure including:
(i) a first module circuit layer on which the first array of DRAM chips are mounted in said module region;
(ii) a first burn-in circuit layer beneath said first module circuit layer, in which a first burn-in circuit is arranged;
(iii) a first ground plane formed between said first module circuit layer and said first burn-in circuit layer;
(iv) a second burn-in circuit layer beneath said first burn-in circuit layer, in which a second burn-in circuit is arranged;
(v) a second module circuit layer beneath said second burn-in circuit layer, on which the second array of DRAM chips are mounted in said module region; and
(vi) a second ground plane formed between said second module circuit layer and said second burn-in circuit layer;
During a burn-in process, a burn-in signal is received and directed by said first burn-in circuit in said first burn-in circuit layer to be transferred through said dummy region of said printed circuit board to said first module circuit layer and subsequently into said first array of DRAM chips; and concurrently the burn-in signal is received and directed by said second burn-in circuit in said second burn-in circuit layer to be transferred through said dummy region of said printed circuit board to said second module circuit layer and subsequently into said second array of DRAM chips.
In order to prevent the so-called antenna effect, the removable dummy region is cut away after the burn-in and testing for the DRAM modules are completed, so as to expose the module pins on the edge of the DRAM module circuit board. Moreover, the DRAM chips can be mounted on the printed circuit board by various methods, such as package assembly, chip-on-board, and bare chip C
4
soldering.
REFERENCES:
patent: 5391892 (1995-02-01), Devereaux et al.
patent: 5461328 (1995-10-01), Devereaux et al.
patent: 5590079 (1996-12-01), Lee et al.
patent: 5886535 (1999-03-01), Budnaitis
Han Charlie
Hsuan Min-Chih
Jaw Jerry
Liu Tung-Chi
Garbowski Leigh Marie
Rabin & Champagne, P.C.
Smith Matthew
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