Preamp writer fault detection circuit

Details Preamp writer fault detection circuit Preamp writer fault detection circuit

1999-03-31

2002-03-05

Tu, Christine T. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error/fault detection technique

C714S819000, C340S661000

Reexamination Certificate

active

06353914

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates to hard drive circuitry, and more particularly relates to an apparatus for detecting an open circuit in a head write driver circuit.
BACKGROUND OF THE INVENTION
Computer hard drive storage units are part of most computer systems. These units include a magnetic head that is maintained at a very small distance from, and directed across the surface of a rotating magnetic disk. The head is controlled to write data to, and read data from the disk.
FIG. 1
is a high level diagram showing basic elements of a typical hard drive unit
10
. A magnetic disk
12
spins on a spindle
14
. An arm
16
is controllably moved about a pivot
18
. The resulting movement causes a magnetic head
22
, which is maintained a small distance from the surface of disk
12
, to move across the disk
12
as shown by arrow
20
. Differential data signals are provided on input lines
24
and
26
to hard drive circuitry
28
. Included in hard drive circuitry
28
is write drive circuitry
30
. Write drive signals are provided from write drive circuitry
30
on lines
32
and
34
to arm
16
, where they are conveyed to magnetic head
22
.
In write operations, differential signals of alternating polarity are provided via lines
32
and
34
to magnetic head
22
so as to magnetize disk
12
in a pattern representing data to be stored in the unit.
When wire
32
and/or wire
34
breaks, an open circuit condition results that prevents data from being written to disk
12
. Obviously, this is undesirable, and as a result fault detection circuits have been devised for detecting such open circuit conditions, so that the user of the hard drive may be alerted to this situation. Such fault detection circuits are typically integrated into the write drive circuitry
30
. One such fault detection circuit is disclosed in U.S. Pat. No. 5,729,208, which issued on Mar. 17, 1998, to Hisao Ogiwara, which is assigned to Texas Instruments Incorporated, and which is hereby incorporated by reference.
FIG. 2
shows a prior art write drive circuit
30
including a fault detection circuit embodying principles from that patent.
FIG. 3
is a signal timing diagram of certain signals used and generated by the circuit of FIG.
2
.
Briefly, referring to both
FIGS. 2 and 3
, differential write data signals D
x
and D
y
, at positive supply emitter coupled logic (“PECL”) levels are provided on lines
42
and
44
, respectively, and are converted to complementary metal oxide semiconductor (“CMOS”) levels in converter
46
. The resulting level-adjusted data signals are inverted by inverters
48
and
50
, respectively, and the resulting inverted data signals are provided as inputs to a write driver
52
and to a CMOS to PECL level converter
54
. The reconverted data signal outputs of converter
54
are used as complementary phase control signals &phgr; and &phgr;, respectively. The outputs of write driver
52
,
32
and
34
, carry the write driver signals H
X
and H
y
, respectively, provided to the hard drive head
22
(FIG.
1
). In
FIG. 2
hard drive head
22
is not shown. However, the inductance L
HEAD
56
seen electrically by the write driver
52
is shown, as it is significant to a discussion of some of the signals shown in
FIG. 3
, as will be made clear below.
Line
32
is provided to one input of a first comparator
58
, and line
34
is provided to one input of a second comparator
60
. The other inputs of both comparators
58
and
60
are connected by a line
59
to the source
62
of a reference voltage V
th
used to set the thresholds of comparators
58
and
60
.
The differential outputs of comparator
58
, carrying signals C
X
and {overscore (C
X
+L )}, are provided to the differential inputs of a latch
64
. The differential clock inputs CK and {overscore (CK)} of latch
64
receive control signals {overscore (&phgr;)} and &phgr;, respectively. The differential outputs of latch
62
, A and {overscore (A)}, are provided to two inputs of a 4-input multiplexer
66
.
The differential outputs of comparator
60
, carrying signals C
y
and {overscore (C
Y
+L )}, are provided to the differential inputs of a latch
68
. The differential clock inputs CK and {overscore (CK)} of latch
68
receive control signals {overscore (&phgr;)} and &phgr;, respectively. The differential outputs of latch
68
, B and {overscore (B)}, are provided to the other two inputs of 4-input multiplexer
66
. Multiplexer
66
receives control signals &phgr; and {overscore (&phgr;)} at the select input thereof.
The differential output of multiplexer
66
is provided to a PECL to CMOS level converter
70
, the output of which is a WRITE OPEN indication signal.
Referring now additionally to
FIG. 3
, the write drive circuit
30
of
FIG. 2
operates as follows. Write data D
X
and D
Y
are logical opposites of one another, where one is high and the other low, and vice versa. D
X
and D
Y
are converted to ECL levels by converter
46
into control signals &phgr; and {overscore (&phgr;)} to be used to clock the latches
64
and
68
and multiplexer circuit
66
. Write driver
52
then generates signals H
X
and H
Y
from the write data, exemplary waveforms of which are shown in FIG.
3
. Comparator
58
compares signal H
X
with reference voltage V
th
, and generates differential output signals, signals C
X
and {overscore (C
X
+L )}. Comparator
60
compares signal H
Y
with reference voltage V
th
, and generates differential output signals, signals {overscore (C
Y
+L )} and C
Y
. The reference voltage V
th
may be chosen to be a little higher than the saturation voltage of the comparators
58
and
60
, which is between one and four volts. Signals C
X
and {overscore (C
X
+L )} are latched by latch
64
, and signals C
Y
and {overscore (C
Y
+L )} are latched by latch
68
, with control signals &phgr; and {overscore (&phgr;)} serving as clock signals. In other words, the write driver data H
X
and H
Y
are latched just before their predetermined polarity change by using, essentially, the rising edges of D
X
and D
Y
as latch clocks.
It will be appreciated that during normal operation, the latch output signals, A and B, are always high or at logic level “one.” This is because the signals C
X
and C
Y
are always latched at a logic “one,” as a consequence of the “rebound” action of inductance L
HEAD
on the signals H
X
and H
Y
. Thus, the WRITE OPEN signal is always high. However, if an open circuit condition occurs, as at time
80
in
FIG. 3
, the inductance L
HEAD
no longer operates on the signals H
X
and H
Y
, and their waveform simply tracks that of D
X
and D
Y
. Consequently a “zero” is latched in one of latches
64
and
68
, in this case a “zero” level of signal C
X
being first latched in latch
64
, and the WRITE OPEN signal goes to zero and remains there.
The foregoing solution has provided very good fault detection operation. However, as data rates of hard drives have increased with the advance of technology, certain problems have arisen in the operation of fault detection circuits like that circuit
30
. Specifically, faults have been indicated when none exist, resulting in an incorrect determination of a failed hard drive unit.
How these faults occur can be better understood by reference to FIG.
4
and
FIG. 5
, which help illustrate two ways in which the circuit of
FIG. 2
generates false fault indications.
FIG. 4
shows two of the signals shown in
FIG. 3
, namely D
X
and H
X
, when the circuit
30
of
FIG. 2
is operated at a high data rate typical for current hard drives. Note that the high level excursions, e.g.,
90
, and low level excursions, e.g.,
92
, of the data pules of D
X
are not of equal duration. After a relatively longer low excursion
94
, at time
96
, which is the occasion of a state latch in latch
64
(FIG.
2
), it can be seen that at the level of H
X
has rebounded to a sufficiently positive level over the threshold level
98
, for the reasons set forth above, so as to latch a “one” in latch
64
, resulting in a WRITE OPEN level indicating no fault. Howev

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