Preamble detection and postamble closure for a memory...

Details Preamble detection and postamble closure for a memory... Preamble detection and postamble closure for a memory...

2011-03-22

2011-03-22

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Read/write circuit

Particular read circuit

C365S193000, C365S194000, C365S154000

Reexamination Certificate

active

07911857

ABSTRACT:
A memory controller, such as a memory controller for reading data received from a DDR SDRAM memory, may detect the beginning and end of a read cycle. The memory controller may include a preamble detection circuit to receive a strobe signal and output a first control signal indicating detection of a preamble window in the strobe signal that indicates a beginning of the read cycle, where the first control signal is delayed based on a selectable delay period applied to the first control signal. The memory controller may further include a first gate to, based on the first control signal, either output the strobe signal for reading of the data lines or block the strobe signal, and the control logic to set an amount of the selectable delay period for the preamble detection circuit.

REFERENCES:
patent: 2005/0024972 (2005-02-01), Schaefer

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