Pre-treatment method performed on a semiconductor structure...

Details Pre-treatment method performed on a semiconductor structure... Pre-treatment method performed on a semiconductor structure...

1999-05-07

2001-05-08

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

C438S664000, C438S665000

Reexamination Certificate

active

06228739

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor integrated circuit, and more particularly, to a pre-treatment method performed on a semiconductor structure before forming hemi-spherical grains (HSGs) on a storage node of a capacitor for a semiconductor integrated circuit.
2. Description of the Related Art
As the techniques for fabricating semiconductor devices become more advanced, memory devices having larger capacities can be produced to meet demand in the ever increasing areas in which semiconductor devices are applied. As the memory circuit becomes more highly integrated with increases in the capacity of the memory of the device, the area of a unit memory cell of the device becomes smaller and the cell capacitance is reduced. For instance, a dynamic random access memory (DRAM) includes a capacitor used as a means of storing information, and a controllable switching transistor for transmitting signals, connected to the capacitor. In such a DRAM, the area of the unit memory cell is so small that the correspondingly low capacitance makes the memory cell difficult to read, and is a significant cause of soft errors.
In the memory cell, the base structure of a capacitor includes a storage electrode, a dielectric layer and a plate electrode. In this case, there are three ways to obtain high capacitance in a small area: a reduction in the thickness of the dielectric layer, an increase in the effective area of the capacitor electrode, and the use of a material having a high dielectric constant as the dielectric layer. However, the thickness of the dielectric layer impacts the performance of the dielectric layer. That is, as the thickness is reduced, the leakage current of the capacitor is increased and the dielectric breakdown voltage is decreased. Thus, the dielectric layer should be thick enough to prevent the leakage current and to sustain a sufficient dielectric breakdown voltage. The effective area of the capacitor electrode depends on the shape of various types of capacitors (e.g., planar, trench, stack, cylinder types) that are used. For higher dielectric constants, the leakage current is less, the dielectric breakdown voltage is high, and the thickness of the layer and the size of the memory cell can be reduced and the capacitance is increased.
Instead of using capacitors having three-dimensional structures, such as trench or cylinder types of capacitors, to increase capacitance, many of today's 16-256 DRAM devices rely upon hemi-spherical grains (HSGs) which are grown on the surface of the storage node. The method for growing HSGs on the surface of the storage node to increase the capacitance involves a process of phase-changing amorphous silicon to polysilicon. Specifically, the amorphous silicon is first deposited on a semiconductor substrate. When the semiconductor substrate where the amorphous silicon is deposited is then annealed, the amorphous silicon grows and changes into polysilicon having a rough surface where fine hemi-spherical grains are present. In the capacitor storage node of the HSG type, the surface area is two or three times larger than that of a conventional flat surface of the same size.
FIG. 1
is a cross-sectional view illustrating a conventional pre-treatment method before forming the HSGs of the storage node.
Referring to
FIG. 1
, sub-structures (not shown) such as a transistor and a bit line are formed on a semiconductor substrate
10
, and an interlayer dielectric film
20
for forming a capacitor is formed thereon. Photolithography and etching processes are then performed on the interlayer dielectric film
20
to form a contact hole exposing a part of the semiconductor substrate
10
. Thereafter, a plug
30
is formed to fill the contact hole. Then, a storage node layer of polysilicon is deposited and patterned to form a storage node pattern
50
. Any etching residue remaining after the patterning process is removed through ashing, using oxygen gas as an etching gas, and a stripping process using H
2
SO
4
. A cleaning process for removing native oxide growing on the surface of the storage node pattern
50
is performed using a cleaning solution including fluoric acid (HF). After this conventional pre-treatment method is completed, amorphous silicon is deposited on the resulting structure and grown to form HSGs (see FIG.
2
).
However, even after performing the cleaning process using HF in an attempt to remove the native oxide on the storage node pattern
50
, an etching residue layer
40
including polymers or particles formed by plasma damage, and remnants of the native oxide layer, still remain on the surface of the storage node pattern
50
.
FIG. 2
is a scanning electronic microscope (SEM) photograph illustrating a case where HSGs are formed by depositing amorphous silicon and annealing the same without the etching residue layer
40
(
FIG. 1
) being removed properly. The etching residue layer
40
prevents a silicon (Si) component from moving around an amorphous silicon seed in the subsequently performed process of growing HSGs. Thus, if the growth of the HSGs is suppressed, the surface area of the storage node pattern
50
fails to increase the effective area of the capacitor electrode. The resultant semiconductor memory device will thus fail to possess the desired high level of capacitance.
SUMMARY OF THE INVENTION
It is an objective of the present invention to provide a pre-treatment method which includes cleaning a storage node pattern before forming HSGs of a capacitor storage node. The pre-treatment method effectively removes polymers remaining on the surface of the storage node pattern and etching residue caused by plasma damage. This is achieved by performing the ashing process in multiple stages using an etching gas capable of removing a native oxide remaining after etching a capacitor storage node pattern, performing a H
2
SO
4
stripping step, and performing a cleaning step using an ammonium peroxide mixture (APM).
Accordingly, to achieve the above and other objectives, there is provided a pre-treatment method performed on a semiconductor structure before HSGs are grown, where the pre-treatment method includes dry-etching a material layer formed on a surface of a semiconductor substrate, with the material layer having a photoresist pattern formed thereon. The dry-etching forms a resultant semiconductor structure comprising a storage node pattern on the semiconductor substrate. Multiple ashing sequences are then performed on the semiconductor structure using an etching gas. The semiconductor structure is stripped using H
2
SO
4
to remove any residue remaining on the semiconductor structure after the multiple ashing sequences. The semiconductor structure is then cleaned with an ammonium peroxide mixture (APM), after which, the HSGs are grown on storage nodes of the storage node pattern.
According to a preferred embodiment of the present invention, the etching gas includes O
2
combined with one of CF
4
and N
2
, depending on the type of material to be removed, with the multiple ashing sequences being performed in situ, that is, in batch type ashing equipment.
Preferably, the multiple ashing sequences are performed in three sub-steps including (1) removing polymers at the sidewalls of the dry-etched storage node pattern, (2) removing the photoresist pattern, and (3) removing both a native oxide layer and a layer produced due to etching damage on the surface of the storage node.
In the ashing sequence of step (1), a gas containing O
2
and CF
4
mixed in a ratio of about 100 to 2.5 is used as an etching gas, with the ashing sequence of step (1) being performed for about 30 seconds at a chamber pressure of 0.8-1.2 Torr, a temperature of 240-260° C. and a power of 920-980 W.
In the ashing sequence of step (2), a gas containing O
2
and H
2
mixed in a ratio of about 100 to 5 is used as an etching gas, with the ashing sequence of step (2) being performed for about 30-50 seconds at a chamber pressure of 0.9-1.3 Torr, a temperature of 240-260° C. and

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