Pre-synthesis test point insertion

Details Pre-synthesis test point insertion Pre-synthesis test point insertion

1999-03-31

2001-10-30

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06311317

ABSTRACT:

FIELD OF THE INVENTION
The field of the present invention pertains to the field of electronic design automation. More particularly, aspects of the present invention pertain to methods and systems for improving testability of an integrated circuit design.
BACKGROUND OF THE INVENTION
Complicated integrated circuits such as ASICs (application specific integrated circuits) and FPGAs (field programmable gate arrays) are typically designed using CAD (computer aided design) tools. The development of complicated integrated circuits with the aid of CAD tools is referred to as electronic design automation, or EDA. Design, checking, and testing of large-scale integrated circuits are so complex that the use of programmed computer systems are required for realization of normal circuits. This is partly because the integrated devices are inherently complex and partly because the circuit design needs to be decomposed into simpler functions which are recognized by the CAD tool. It is also partly because considerable computation is required in order to achieve an efficient implementation of the resultant network. The result of the computerized design process is a detailed specification defining a complex integrated circuit in terms of a particular technology. This specification can be regarded as a template for the fabrication of the physical embodiment of the integrated circuit using transistors, routing resources, etc.
Integrated circuit designs can be represented in different levels of abstraction, such as the register transfer level (RTL) and the logical level, using a hardware description language (HDL), also called high level design language. Two exemplary forms of HDL are Verilog and VHDL. The integrated circuit can be represented by different layers of abstractions (e.g., behavioral levels, structural levels and gate levels). An RTL level is an intermediary level of abstraction between the behavioral and structural levels. HDL descriptions can represent designs of all these levels.
The behavior levels and RTL levels consist generally of descriptions of the circuit expressed with program-like constructs, such as variables, operators conditional loops, procedures, and functions. At the logic level, the descriptions of the circuit are expressed with Boolean equations. The HDL can be used along with a set of circuit constraints as an input to a computer-implemented compiler (also called a “silicon compiler”). The computer-implemented compiler program processes this description of the integrated circuit and generates therefrom a detailed list of logic components and the interconnections between these components. This list is called a “netlist.” The components of a netlist can include primitive cells such as full-adders, NAND gates, NOR gates, XOR gates, latches, and D-flip flops, etc., and their interconnections can be used to form a custom design.
In processing the HDL input, the compiler first generates a netlist of generic primitive cells that are technology independent. The compiler then applies a particular cell library to this generic netlist (this process is called mapping) in order to generate a technology-dependent mapped netlist. The mapping process converts the logical representation which is independent of technology into a form which is technology dependent. The mapped netlist has recourse to standard circuits, or cells, which are available within a cell library forming a part of the data available to the computer system.
Compiler programs and mapping programs are well known in the art, and several of these systems are described in U.S. Pat. No. 5,406,497, by Altheimer et al.
As ASICs and other complex integrated circuits have become more complex and more dense, they have become progressively harder to test in order to ensure correct and complete functionality. For example, with current technology, as the number of gates and transistors increase, the time which an ASIC emerging from a fabrication process line spends in testing increases as well. This increase incurs an additional cost on ASIC manufacturing. The testing cost can be very significant for the latest and largest ASIC designs. In addition, as more complex systems-on-a-chip devices proliferate, which, for example, integrate complex logic units (integer units, floating point units, memory, etc.) into a single chip, and as newly-designed processors begin to take advantage of the ability to integrate large quantities of memory on-chip, it has become necessary to increase the comprehensiveness, efficiency, and accuracy of the design checking and testing schemes utilized to ensure proper operation of these devices (e.g., ASICs, complex integrated circuits, field programmable gate arrays, etc.).
Thus, an increasingly important part of the logic synthesis process involves designing for testability. Programs that aid in the testability process of logic synthesis are called design for test (DFT) processes. One approach to DFT is to take the mapped netlist generated from a compiler and add and/or replace certain memory cells and associated circuitry with special memory cells that are designed to allow the application of test vectors to certain logic portions of the integrated circuit. The act of applying test vectors is called stimulation of the design, and the special memory cells and associated circuitry are referred to as DFT implementations. The same memory cells can be used to capture the output of the circuitry for observation and compare this output to the expected output in an effort to determine if circuit (e.g., manufacturing) defects are present. Issues concerning controllability deal with facilitating the application of the test vectors to the circuitry to be tested. On the other hand, issues concerning observability deal with facilitating the capturing the output of the circuitry.
Another approach to DFT is to take the mapped netlist generated form the compiler, and insert observe/control points, or test points, to certain logic portions of the integrated circuit design. Appropriate test vectors are then applied to the input of the integrated circuit design and to the test points and the responses to the test vectors are monitored. Observe points are particularly useful for detecting otherwise unobservable faults. For example, in the circuit
100
illustrated in
FIG. 1A
, it may be impossible to detect a fault (e.g., a stuck-at-0 fault) at an internal node
102
from the circuit output. As illustrated in
FIG. 1B
, by incorporating an observe point at the internal node
102
, a specific input pattern may be applied to the circuit
100
to detect the fault.
FIGS. 2A and 2B
illustrate the usefulness of adding a control point within a circuit. As shown in
FIG. 2A
, it may be impossible to detect a stuck-at-1 fault with the X-NOR gate
210
of the circuit
200
if the outputs of the logic block
220
are always the same. This problem may be circumvented by the addition of a control point to the circuit
200
. A modified circuit
250
including an AND gate
230
is illustrated in FIG.
2
B. During normal operation, the control input of the AND gate
230
is set at logic 1. To test for a stuck-at-1 fault at the output of the X-NOR gate, the control input of the AND gate
230
is set at logic 0 and an input combination that produces logic 1 at the outputs of the logic block
220
is applied. In this way, the testability of the circuit
200
is improved.
An exemplary flow chart diagram of a typical logic synthesis process, including a DFT process, is shown in FIG.
3
. The processes
300
described with respect to this flow chart are implemented within a computer system in a CAD environment. HDL descriptions of the integrated circuit enter at block
301
. Accompanying the HDL
301
is a set of performance constraints
305
applicable to the design which typically includes timing, area, power consumption, and other performance related limitations that the compiler
325
will attempt to satisfy when synthesizing the integrated circuit design. Constraints
305
can also include non-performance related constraints, such as

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