Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2001-09-14
2003-12-16
Chen, Kin-Chan (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S700000
Reexamination Certificate
active
06664190
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a method of fabricating semiconductor structures, and more particularly, to a method of forming planarized shallow trench isolation structures in the manufacture of integrated circuit devices.
(2) Description of the Prior Art
Shallow trench isolation (STI) is now commonly used in the art as an alternative to local oxidation of silicon (LOCOS) for forming isolations between active device areas in the integrated circuit. STI offers the advantages of smaller isolation area and better surface planarization when compared to LOCOS. However, the STI process suffers from dishing, especially over large trenches. Dishing can cause excessive device leakage in some cases.
Several prior art approaches disclose methods to form and planarize shallow trench isolations. U.S. Pat. No. 6,197,691 to Lee shows a chemical mechanical polishing (CMP) process using silicon nitride as an etch stop layer. U.S. Pat. No. 5,712,185 to Tsai et al and U.S. Pat. No. 5,736,462 to Takahashi et al show processes in which a polysilicon layer over a silicon nitride layer is used as an etch stop for CMP. U.S. Pat. No. 5,173,439 to Dash et al and U.S. Pat. No. 4,962,064 to Haskell et al teach using polysilicon as a mask over wide trenches. U.S. Pat. No. 4,954,459 to Avanzino et al, U.S. Pat. No. 5,961,794 to Morita, and U.S. Pat. No. 6,015,755 to Chen et al teach reverse mask processes. U.S. Pat. No. 6,103,581 to Lin et al discloses a non-crystalline silicon hard mask layer. U.S. Pat. No. 6,146,974 to Liu et al shows STI process.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of fabricating shallow trench isolations in the manufacture of integrated circuits.
A further object of the present invention is to provide a method to fabricate planarized shallow trench isolations.
Another object of the present invention is to provide a method to fabricate planarized shallow trench isolations using a reverse mask process for chemical mechanical polishing (CMP).
Yet another object of the invention is to provide a method to fabricate planarized shallow trench isolations using polysilicon or amorphous silicon as a reverse mask etch stop for chemical mechanical polishing (CMP).
In accordance with the objects of this invention, a new method of forming shallow trench isolations using a reverse mask process is achieved. A polish stop layer is deposited on the surface of a substrate. An etch stop layer is deposited overlying the polish stop layer. A plurality of isolation trenches is etched through the etch stop layer and the polish stop layer into the substrate whereby narrow active areas and wide active areas of the substrate are left between the isolation trenches. An oxide layer is deposited over the etch stop layer and within the isolation trenches. The oxide layer is covered with a mask in the narrow active areas and in the isolation trenches and etched away in the wide active areas stopping at the etch stop layer. Thereafter, the mask is removed and the etch stop layer is polished away to the polish stop layer whereby the oxide layer in the isolation trenches is planarized to complete planarized shallow trench isolation regions in the manufacture of an integrated circuit device.
REFERENCES:
patent: 4954459 (1990-09-01), Avanzino et al.
patent: 4962064 (1990-10-01), Haskell et al.
patent: 5173439 (1992-12-01), Dash et al.
patent: 5494857 (1996-02-01), Cooperman et al.
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patent: 5923993 (1999-07-01), Sahota
patent: 5961794 (1999-10-01), Morita
patent: 5998297 (1999-12-01), Brennan
patent: 6015755 (2000-01-01), Chen et al.
patent: 6015757 (2000-01-01), Tsai et al.
patent: 6103581 (2000-08-01), Lin et al.
patent: 6103594 (2000-08-01), See et al.
patent: 6146974 (2000-11-01), Liu et al.
patent: 6169012 (2001-01-01), Chen et al.
patent: 6197691 (2001-03-01), Lee
patent: 6303461 (2001-10-01), Chen et al.
patent: 6448159 (2002-09-01), Chen et al.
Chen Feng
Loh Cheng-Hou
Proctor Paul
Chartered Semiconductor Manufacturing Ltd.
Chen Kin-Chan
Pike Rosemary L. S.
Saile George O.
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