Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2007-07-17
2007-07-17
Peugh, Brian R. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S217000
Reexamination Certificate
active
10368751
ABSTRACT:
The present invention realizes pre-fetch based on a high-accuracy prediction. A plurality of address values are registered in advance in a pre-fetch address queue, based on previous memory accesses. If a request address from the processor unit of a request address register matches this address value, a pre-fetch address obtained by adding a block size to the request address is output to a secondary cache as a pre-fetch request. This pre-fetch address is written back into the pre-fetch address queue.
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Inoue Aiichiro
Motokurumada Tsuyoshi
Shirahige Yuji
Ukai Masaki
Fujitsu Limited
Peugh Brian R.
Staas & Halsey , LLP
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