Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Patent
1997-12-08
2000-08-08
Bowers, Charles
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
438622, 438637, 438704, 438705, 438723, 438735, 438745, 438749, 438756, 438778, 438783, 438784, H01L 214763, H01L 21302, H01L 21461, H01L 2131, H01L 21469
Patent
active
06100202&
ABSTRACT:
A chemical vapor deposition (CVD) method for forming a doped silicate glass dielectric layer within a microelectronics fabrication. There is first positioned within a reactor chamber a substrate employed within a microelectronics fabrication. There is then stabilized within the reactor chamber with respect to the substrate a first flow of a silicon source material absent a flow of a dopant source material. There is then deposited upon the substrate within the reactor chamber a doped silicate glass dielectric layer through a chemical vapor deposition (CVD) method. The doped silicate glass dielectric layer is formed employing a second flow of the silicon source material, a flow of an oxidant source material and the flow of the dopant source material. There may subsequently be formed through the doped silicate glass dielectric layer an anisotropically patterned via through an anisotropic patterning method. The anisotropically patterned via may then be isotropically etched to form an isotropically etched anisotropically patterned via without void formation within the sidewalls of the isotropically etched anisotropically patterned via.
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Lin Been-Hon
Liu Chung-Chieh
Peng Bing-Huei
Akerman Stephen B.
Bowers Charles
Pham Tanhha
Saile George O.
Szecsy Alek P.
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