Pre-decode conditional command generation for reduced SDRAM...

Details Pre-decode conditional command generation for reduced SDRAM... Pre-decode conditional command generation for reduced SDRAM...

1998-12-04

2002-08-27

Yoo, Do Hyun (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C365S230060, C365S239000

Reexamination Certificate

active

06442645

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to memory controllers, and specifically, to a method and apparatus for improving the performance of SDRAM-based memory subsystems by reducing, in most cases, the latency of a cycle from any bus-mastering agent to memory.
2. Background Information
Memory controllers provide an interface between one or more bus masters and a memory subsystem (e.g., synchronous dynamic random access memory, “SDRAM” array). A bus master is an electronic device that initiates a transaction to a destination unit. Such bus masters include, for example, the host processor, a graphics device, and an input/output device, to name a few. The bus masters randomly issue requests to the SDRAM array. These requests typically pass through the memory controller in a serial fashion.
Current memory controllers fully decode an incoming address and based on this complete decode, determine the type of command that is to be issued to the SDRAM array, and when it is safe to issue such command. This complete decode is time consuming. Waiting for its completion typically results in delaying the assertion of a command to the SDRAM array. The information decoded includes the row and bank a cycle is targeting, the page-hit, page-miss, and row-miss statuses, and whether the cycle is to the same row and/or same bank as the previous cycle. Based on this complete decode, the memory controller generates the appropriate commands on the row address strobe, column address strobe, and write enable pins. In addition, the memory controller drives the appropriate row or column addresses on the memory address pins, and then asserts a signal on the chip select pin for the physical row of memory that is addressed. In high frequency, large memory systems, the above-mentioned decode can take two or more clocks to complete before the signal on the chip select pin can be asserted. This is time consuming, especially since millions of such decodes may occur in a second.
Accordingly, there is a need in the technology for a method and apparatus for reducing SDRAM cycle latency.
SUMMARY OF THE INVENTION
The present invention comprises a method and apparatus for reducing latency of a cycle initiated by a bus-mastering agent to memory. In one embodiment, the method includes receiving a memory request, partially decoding the memory request, sampling one or more safe indicator signals, and causing a chip select signal to be asserted without knowing a cycle type of the memory request, responsive to the partial decode and the one or more safe indicator signals.


REFERENCES:
patent: 4236205 (1980-11-01), Kindseth et al.
patent: 4429374 (1984-01-01), Tanimura
patent: 5485589 (1996-01-01), Kocis et al.
patent: 5691956 (1997-11-01), Chang et al.

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