Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2011-08-02
2011-08-02
Doan, Duc T (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
Reexamination Certificate
active
07991964
ABSTRACT:
A cache architecture to increase communication throughput and reduce stalls due to coherence protocol dependencies. More particularly, embodiments of the invention include multiple cache agents that each communication with the same protocol agent. In one embodiment, a pre-coherence channel couples the cache agents to the protocol agent to enable the protocol agent to receive events corresponding to cache operations from the cache agents to maintain ordering with respect to the cache operation events.
REFERENCES:
patent: 6009488 (1999-12-01), Kavipurapu
patent: 6735675 (2004-05-01), Breuder et al.
patent: 6865695 (2005-03-01), Joyner et al.
patent: 2003/0126365 (2003-07-01), Jamil et al.
Blakely , Sokoloff, Taylor & Zafman LLP
Doan Duc T
Intel Corporation
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