Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2001-08-29
2003-06-17
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S203000, C365S205000, C365S230060
Reexamination Certificate
active
06580655
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices, such as dynamic random access memory (DRAM), that use sense amplifiers shared between right and left arrays of memory cells and connected to those arrays through isolation transistors. More specifically, the present invention relates to the circuit that controls the isolation transistors during pre-charging and to the method of pre-charging the shared sense amplifier in such memory devices.
2. Description of Related Art
Memory devices designed with shared sense amplifiers have two bitline pairs that are typically located on opposite (left and right) sides of the sense amplifier they share. Before a memory cell can be accessed, the bank containing that cell must be activated. To access the left bank of memory cells, the sense amplifier is connected to the left side bitline pair through a corresponding pair of left side isolation transistors. As the left side isolation transistors are turned on, the sense amplifier is simultaneously disconnected from the unused right side bitline pair by turning off isolation transistors on the right side. To access a memory cell in the right bank the opposite occurs: the right side isolation transistors are turned on and the left side isolation transistors are turned off.
Each time a new bank is to be accessed, a bank activation command is issued to select a new row of cells and start a new row cycle. Between each row cycle the shared sense amplifier must be pre-charged through the bitlines to an equalization voltage (intermediate between the high and low voltage states). A conventional design for the circuit used to control the isolation transistors during pre-charging (the pre-charge circuit) simultaneously turns on the isolation transistor pairs on both sides of the shared sense amplifier.
This conventional pre-charge circuit design has a significant disadvantage, however, in that a pre-charge failure on either side of the sense amplifier may cause a failure on the opposite side due to the simultaneous connection of both sides to the sense amplifier. For example, if a wordline on one side of the sense amplifier is shorted to a bitline on that side, this conventional pre-charge circuit design causes a reduction in the equalization voltage on the opposite side of the sense amplifier as well as on the failed side. This reduction in equalization voltage causes the opposite side to fail, resulting in two failures as a result of the single defect.
An improved pre-charge circuit is presently in use in which the sense amplifier is pre-charged to the equalization voltage from only one side. The choice of the side to use for pre-charging is arbitrary because the location of any defect is unknown. Approximately half of the time, the location of the defect will be on the opposite side of the sense amplifier from the side that is used for pre-charging, allowing the pre-charge side to operate correctly without being affected by the defect.
This improved pre-charge design has heretofore always been implemented by pre-charging the sense amplifier from the same pre-selected side (the pre-charge side) between each row cycle. For the case in which the previous row operation took place on the pre-charge side of the sense amplifier, the two pairs of isolation transistors will already be in the correct state (pre-charge side on and non-pre-charge side off) for pre-charging. However, after a row operation to the non-pre-charge side, all four of the isolation transistors must change state to disconnect the bitline pair from the non-pre-charge side and connect the bitline pair on the pre-charge side.
If the non-pre-charge side is to be accessed a second time, the four isolation transistors must be switched yet again to reconnect the non-pre-charge side to the sense amplifier. The isolation transistors must be switched at the proper time and in the proper sequence relative to the other memory control signals to connect the sense amplifier to the pre-charge side before pre-charging. Switching the isolation transistors after each row operation to the non-pre-charge side, and the necessity to fit this timing event into the other timing events related to the row cycle lengthens the duration of each row cycle. It would be desirable to be able to eliminate this pre-charge timing event.
A more significant problem, however, relates to the difficulty in turning off the isolation transistors on the low bitline on the non-pre-charge side after a row operation to that side. The isolation transistors on the pre-charge side and the isolation transistor on the high bitline on the non-pre-charge side all switch quickly. However, after a row operation to the non-pre-charge side, the transistor on the low bitline on that side does not turn off until the isolator transistors on the pre-charge side begin to turn on.
During this period, charge leaks onto the low bitline, raising it above its initial low voltage level. During equalization, the two bitlines on the non-pre-charge side are connected and the charge on the low bitline is shared with the high bitline, resulting in the bitline pair on the non-pre-charge side having a higher voltage than the desired midpoint equalization voltage. This offset from the intended equalization voltage is undesirable and can result in read errors.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a pre-charge circuit for use in shared sense amplifier memory devices that includes the advantages of prior art improved pre-charge circuit designs relative to defects, but which also eliminates the equalization problem described above.
It is another object of the present invention to provide a pre-charge circuit for use in shared sense amplifier memory devices that eliminates one timing event during the pre-charge cycle.
It is a further object to simplify the circuit controlling the isolation transistors during pre-charge and memory bank activation.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
SUMMARY OF THE INVENTION
The present invention is directed to a new pre-charge circuit design and a new method of controlling the isolation transistors during pre-charging of a shared sense amplifier. It is based upon the recognition that the sense amplifier can be pre-charged from either side, and it is not necessary to pre-charge from the same side every time.
The equalization problem discussed above only occurs when pre-charging from the side opposite the previous row operation. It is possible to always pre-charge from the side used in the previous row operation, thereby eliminating the equalization problem discussed above. This has the additional substantial advantage that the isolation transistors are automatically in the correct state for pre-charging. They do not have to be switched to a predetermined state for pre-charging.
Consequently, it is not necessary to wait for the isolation transistors to switch prior to pre-charging. Because there is no timing event related to switching the isolation transistors for pre-charging, and no timing tolerance is required for this event, subsequent timing events can begin sooner, thereby improving performance.
The present invention is directed to, in a first aspect, a pre-charge circuit for a memory device having a sense amplifier shared between a right bank during row operations to the right bank and a left bank during row operations to the left bank. Right and left bank isolation transistor pairs are connected between the sense amplifier and the right and left banks, respectively. Corresponding right and left bank isolation control lines are used to control the right and left bank isolation transistor pairs. The right and left bank isolation control lines are switchable by the memory device between on and off states to turn the isolation transistor pairs on and off.
A flip-flop, switchable between a right bank state and a left bank state, includes a r
Jacunski Mark D.
Killian Michael A.
DeLio & Peterson LLC
Ho Hoai
Schnurmann N. Daniel
LandOfFree
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