Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
2006-07-04
2006-07-04
Chambliss, Alonzo (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C257S783000, C438S114000, C438S459000, C438S460000
Reexamination Certificate
active
07071572
ABSTRACT:
Multi-purpose planarizing/back-grind/pre-under-fill arrangements for bumped wafers and dies, in which a planarizing coating provides improved and continued surface protection to the circuit surface of a wafer or die throughout back-grinding and subsequent mounting operations, and provides improved stiffening/strengthening of the wafer and die throughout back-grinding and subsequent mounting operations.
REFERENCES:
patent: 6060373 (2000-05-01), Saitoh
patent: 6107164 (2000-08-01), Ohuchi
patent: 6338980 (2002-01-01), Saitoh
patent: 6342434 (2002-01-01), Miyamoto et al.
patent: 6347947 (2002-02-01), Ong
patent: 6465330 (2002-10-01), Takahashi et al.
patent: 6506681 (2003-01-01), Grigg et al.
patent: 6649445 (2003-11-01), Qi et al.
patent: 6777313 (2004-08-01), Takyu et al.
patent: 6794751 (2004-09-01), Kumamoto
patent: 2001/0036711 (2001-11-01), Urushima
patent: 2002/0068453 (2002-06-01), Grigg et al.
patent: 2002/0166625 (2002-11-01), Ball et al.
patent: 11320962 (1999-11-01), None
patent: WO 02/23592 (2002-03-01), None
Chambliss Alonzo
Green Blayne D.
LandOfFree
Pre-back-grind and underfill layer for bumped wafers and dies does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Pre-back-grind and underfill layer for bumped wafers and dies, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pre-back-grind and underfill layer for bumped wafers and dies will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3535897