PRAMs having a plurality of active regions located...

Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular signal path connections

Reexamination Certificate

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Details

C257S209000, C257S326000, C257S758000, C257SE21021, C257SE21421

Reexamination Certificate

active

11246863

ABSTRACT:
There are provided PRAMS having a plurality of active regions located vertically in sequence and methods of forming the same. The PRAM and the method provide an approach to rapidly changing phase in a phase change layer pattern with a given design rule. A semiconductor substrate defining at least one reference active region is prepared in a cell array region and a peripheral circuit region. Other semiconductor substrates on a vertical line passing a main surface of the reference active region are located in sequence. The other semiconductor substrates define other active regions, respectively. A lower cell gate pattern is formed on the semiconductor substrate of the reference active region, and upper cell gate patterns are disposed on the other semiconductor substrates of the other active regions, respectively.

REFERENCES:
patent: 5998873 (1999-12-01), Blair et al.
patent: 6429484 (2002-08-01), Yu
patent: 6740921 (2004-05-01), Matsuoka et al.
patent: 7038261 (2006-05-01), Horii
patent: 2003-092390 (2003-03-01), None
patent: 2002-0076460 (2002-10-01), None

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