Practical methodology for early buffer and wire resource...

Details Practical methodology for early buffer and wire resource... Practical methodology for early buffer and wire resource...

2006-02-07

2006-02-07

Rodriguez, Paul L. (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

C716S030000, C716S030000

Reexamination Certificate

active

06996512

ABSTRACT:
A method, system, and computer program product for allocating buffer and wire placement in an integrated circuit design is provided. In one embodiment, the surface of a integrated circuit design is represented as a tile graph. Allocation of buffer locations for selected tiles in the tile graph is then received and nets are routed between associated sources and sinks. Buffer locations within selected tiles are then selectively assigned based upon buffer needs of the nets, wherein the nets are routed through selected tiles and assigned buffer locations using a cost minimization algorithm.

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Cheng-Kok Koh, Paterick H, Madden, “Manhatten or Non-Manhatten? A Study of Alternative VLSI Routing Architectures”, ACM 2000, pp. 47-52.

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