Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-01-10
2006-01-10
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06986109
ABSTRACT:
The invention provides a method of modifying a hierarchical integrated circuit layout wherein the locations of hierarchical layout elements are represented with variables and formulae using these variables, which produces a formula-based hierarchical layout. These variables are constrained to be integers. The invention provides for a method for guiding the modification of the layout through an objective function defined on the same variables as the formula-based hierarchical layout. The invention simplifies the formula-based hierarchical layout by substituting constants for some of the variables, such that each of the formulae are reduced to expressions involving no more than two remaining variables. This produces a simplified layout equation and a simplified objective function. This also produces a partial solution to the hierarchical layout modification made up of the values selected for the constants.
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Allen Robert J.
Heng Fook-Luen
Lvov Alexey Y.
McCullen Kevin W.
Peri Sriram
Dimyan Magid Y.
International Business Machines - Corporation
McGinn & Gibb PLLC
Richard Kotulak, Esq.
Smith Matthew
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