Power up detection circuit

Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator

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Details

365226, 365229, 3072723, 3072962, G11C 700

Patent

active

053454227

ABSTRACT:
A circuit for producing a power up detection signal for use in, and being integrated onto the same semiconductor substrate as a dynamic memory device is disclosed. The circuit has a first node and a circuit to promote a low voltage on the first node when a voltage obtained from a supply voltage applied to the dynamic memory is below a predetermined level. It has a second node from which the power up detection signal can be removed. Included is a circuit to promote the obtained voltage on said second node when the obtained voltage is below the predetermined level, whereby the power up detection signal can be used to isolate the obtained voltage from the dynamic memory device. Included is a circuit to maintain a high voltage on the first node when the obtained voltage exceeds the predetermined level. Also included is a circuit to maintain the voltage on the second node at a low state when the high voltage appears on the first node, whereby the power up detection signal can be used to apply to obtained voltage to said dynamic memory device.

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