Electronic digital logic circuitry – Tri-state – With field-effect transistor
Reexamination Certificate
2003-03-14
2004-12-14
Cho, James H. (Department: 2819)
Electronic digital logic circuitry
Tri-state
With field-effect transistor
C326S045000, C326S085000
Reexamination Certificate
active
06831481
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to Programmable Logic Devices (PLDs). More particularly, the invention relates to power-up and enable control circuits for interconnection arrays in PLDDs
BACKGROUND OF THE INVENTION
Programmable logic devices (PLDs) are a well-known type of digital integrated circuit that can be programmed to perform specified logic functions.
FIG. 1
is a simplified illustration of one type of PLD, the Field Programmable Gate Array (FPGA). An FPGA typically includes an array of configurable logic blocks (LBs
101
a
-
101
i
) and programmable input/output blocks (I/Os
102
a
-
102
d
). The LBs and I/O blocks are interconnected by a programmable interconnection array that includes a large number of interconnect lines
103
interconnected by programmable interconnect points (PIPs
104
, shown as small circles in FIG.
1
). PIPs are often coupled into groups (e.g., group
105
) that implement multiplexer circuits selecting one of several interconnect lines to provide a signal to a destination interconnect line or logic block. Some FPGAs also include additional logic blocks with special purposes (not shown), e.g., DLLs, RAM, and so forth.
The interconnection array, LBs, I/O blocks, and other logic blocks are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the interconnection array and logic blocks are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
FIG. 2
is a simplified illustration of another type of PLD called the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more logic blocks (LBs
201
a
-
201
h
) connected together and to input/output blocks (I/Os
202
a
-
202
f
) by a programmable interconnection array (
203
). Each logic block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. The interconnection array includes many multiplexer circuits
205
, each including several PIPs
204
. In each multiplexer circuit
205
, only one PIP
204
is enabled. The enabled PIP selects one of the many input signals provided to the interconnection array, and the selected input signal is provided as the output signal from the multiplexer circuit
205
.
In some CPLDs, configuration data is stored on-chip in non-volatile memory. In other CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
For all of these programmable logic devices (PLDs), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static RAM cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
PLD interconnection arrays typically include large numbers of multiplexer circuits that implement the programmable paths between the logic blocks.
FIG. 3
illustrates several of these multiplexer circuits
301
-
303
, selecting from among the signals on interconnect lines IN
0
-INn. (In the present specification, the same reference characters are used to refer to terminals, signal lines, and their corresponding signals.)
In many PLD applications, large numbers of these multiplexer circuits (and the resources driven by the multiplexer circuits) are not used even when the PLD is configured. Thus, to prevent floating nodes from occurring in a configured PLD, it is desirable for unused multiplexer circuits to provide a known value of either one (power high) or zero (ground). Further, after power-up but prior to configuration of the PLD, the multiplexer circuits preferably also provide a known value. Finally, some known multiplexer circuits also accept an enable signal, which either enables the circuit, or, alternatively, disables the circuit by forcing the multiplexer output signal to a known value. This enable signal allows the multiplexer circuits to be disabled during power-up, for example. Thus, multiplexer circuits in PLD interconnection arrays often include power-up and enable control circuits to provide some or all of these functions.
FIG. 4
is a schematic diagram of a known power-up control circuit that can be used in a PLD interconnection array. The control circuit of
FIG. 4
includes a multiplexer circuit
401
. The contents of memory cells SRAM_
0
-SRAM_m control transistors T_
0
-T_m to select one of the input signals IN_
0
-IN_m, and to place the selected signal on output terminal MUX_OUT. Coupled between output terminal MUX_OUT and power high VCC is a pull-up PU. A configuration memory cell SRAM_PU drives inverter IPU, which in turn controls pull-up PU. Coupled between output terminal MUX_OUT and ground GND is a pull-down PD. A configuration memory cell SRAM_PD drives inverter IPD, which in turn controls pull-down PD.
The control circuit of
FIG. 4
functions as shown in Table 1.
TABLE 1
SRAM_PU
SRAM_PD
SRAM_0
SRAM_1
SRAM_2
SRAM_m
MUX_OUT
0
0
0
0
0
0
0 (blank
device)
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
in_0
0
1
0
1
0
0
in_1
0
1
0
0
1
0
in_2
0
1
0
0
0
1
in_m
In this example, in a blank (unconfigured) device, the contents of all memory cells are zero. Thus, pull-up PU is disabled, and pull-down PD is enabled, pulling output terminal MUX_OUT low. An output terminal that is low by default is generally preferred for a control circuit in a PLD interconnection array, because configuration of the PLD can occur at very low values of power high VCC. Further, to reduce die size both pull-up PU and pull-down PD are preferably minimum-sized devices. Because an N-channel transistor has a lower resistance than a similarly-sized P-channel transistor, pull-down PD is generally faster than pull-up PU. Therefore, the initialization process takes place more rapidly when the default or blank value is zero.
As previously described, typically in a blank PLD all memory cells store zero (low) values. However, as power is first applied to the PLD (i.e., during “power-up”) the memory cells can “wake up” in either state. Therefore, when the circuit of
FIG. 4
is used, during power-up some control circuits are driving high values while others are driving low values. Contention can occur, with the consequent undesirable current flow and even, potentially, resulting damage to the PLD. Therefore, an enable signal is often provided to disable the control circuit until after power-up, as in the circuit of FIG.
5
.
The power-up and enable control circuit of
FIG. 5
includes an enable terminal IA_ENB. When signal IA_ENB is high (e.g., during power-up), output signal MUX_OUT is forced low. When signal IA_ENB is low (e.g., after power-up is complete), the memory cells control the operation of the circuit as described in connection with the circuit of FIG.
4
.
The control circuit of
FIG. 5
includes a multiplexer circuit
501
, which includes memory cells SRAM_O-SRAM_m, inverters I_
0
-I_m, NOR gates N
—0-N
_m, and transistors T_
0
-T_m. When enable signal IA_ENB is low, the contents of memory cells SRAM_
0
-SRAM_m control transistors T
—0-T
_m to select one of the input signals IN_
0
-IN_m, and to place the selected signal on output terminal MUX_OUT. When enable signal IA_ENB is high, all of transistors T_
0
-T_m are disabled (off), and multiplexer circuit
501
does not drive circuit output terminal MUX_OUT.
Coupled between output terminal MUX_OUT and power high VCC is a pull-up PU. A configuration memory cell SRAM_PU drives inverter SPU, which, when enable signal IA_ENB is low, controls pull-up PU through NOR gate NOPU and inverter IPU. When enable signal IA_ENB is high, pull-up PU is off. Coupled between output terminal MUX_OUT and ground GND is a pull-down PD. A configuration memory cell SRAM_PD drives inverter SPD, which, when enable signal IA_ENB is low, controls pull-down PD thro
Lakkapragada Shankar
Nguyen Andy T.
Cartier Lois D.
Cho James H.
Xilinx , Inc.
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