Power supply wiring for semiconductor device

Active solid-state devices (e.g. – transistors – solid-state diode – Contacts or leads including fusible link means or noise...

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257532, 257758, 257760, H01L 2358, H01L 2362

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active

055980295

ABSTRACT:
Ground lines 2 are disposed so as to sandwich a power supply line 1. A gate oxide film 3 and a gate 4 are formed below the power supply line 1. An n-type area 8 is formed adjacent to the end of the gate oxide film to set the ground potential thereto. A p-type area 9 is formed at most of the remaining part below the ground line to make it contact the substrate. Since the potential of the gate equals that of the power source, an inversion layer is formed below the oxide film, where the ground potential results through the n-type area. By sandwiching the gate oxide film between the gate and the inversion layer, a capacitor is formed. The size of the capacitor is half in length as large as the width of the power supply wiring, and the width substantially equals the length of the power supply wiring, the parasitic resistance generated at the gate or inversion layer is suppressed small, and the gate capacitance approximately corresponding to the area of master power supply wiring is interposed between the power source and the ground. As a result, a large capacitance bypass capacitor can be formed between the power source and the ground, and a power supply wiring which is great in effect of eliminating power supply noise can be obtained.

REFERENCES:
patent: 4654689 (1987-03-01), Fujii
patent: 4737830 (1988-04-01), Patel et al.
patent: 4825276 (1989-04-01), Kobayashi
Patent Abstracts of Japan, vol. 13, No. 277, 26 Jun. 1989.
Digest of Technical Papers, 1990 IEEE International Solid-State Circuits Conference, pp. 48, 263 and slide supplement, p. 36 No Month.

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