Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-02-05
2004-06-08
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C703S018000, C702S064000, C702S065000
Reexamination Certificate
active
06748572
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a power supply network analysis of a circuit device, and, more particularly, to an analysis of a power supply network of a large-scale semiconductor integrated circuit device.
2. Description of Related Art
Recently, higher performance and complexity of functions are demanded as the scale of circuits mountable in a semiconductor integrated circuit device increases in accordance with the miniaturization of the fabrication process. As a result, the scale of circuits mountable in a semiconductor integrated circuit device becomes larger and larger and the operational frequency becomes higher. To meet those demands, it becomes necessary to supply larger power source currents with the limited circuit layout area and operational timings. It is therefore important to inspect whether or not power supply lines can secure the supply of power necessary and sufficient for the individual circuit operations.
Performing this inspection is a power supply network analysis. A power supply network is an equivalent circuit which has resistors provided on power supply lines as resistor elements, has circuit elements, which consume currents, converted to current sources and has the current sources connected to connection nodes on the power supply lines to which the circuit elements are connected. Voltage values at the individual connection nodes on the power supply lines to which the circuit elements are connected and values of currents flowing across resistor elements that connect the nodes are acquired by solving the equivalent circuit. By examining the acquired voltage values and current values, it is possible to inspect whether or not the values of voltages to be supplied to the circuit elements connected to the individual nodes are fully sufficient, the currents flowing in the individual power supply lines are sufficient for the electromigration resistance and the reliability over a long operation can be guaranteed.
The following will discuss several methods that have conventionally been performed as power supply network analyses.
The first method is to replace basic elements, such as transistors, as circuit elements with current sources and extract a net list of a power supply network. This method was employed in the early stage of power supply network analysis. This method can accurately analyze a power supply network in case where the circuit scale is small.
The second method is to convert a collection of basic circuit units, such as logic gates, as a circuit cell, into a single current source. As this method can perform a power supply network analysis on the internal interconnection lines of a circuit cell without using a net list, the method is effective when adapted to a power supply network analysis on a larger circuit scale than is involved in the first method.
The third method is to omit a part of the net list of a circuit block constructed by using a plurality of circuit cells as defined in the second method and arrange the net list into a simple net list. One example of simplifying a net list using the third method is disclosed in, for example, Japanese Unexamined Patent Publication No. 2000-57186. The disclosed method comprises the step of extracting data on the widths of individual power supply terminals from layout data of a circuit block and the step of setting ratios of the individual widths to ratios of the amounts of currents consumed at the individual power supply terminals based on the data on the widths of the individual power supply terminals, and estimates the values of source currents to the individual power supply terminals from the ratios and the sum of the values of source currents to the circuit block. In other words, the third method estimates the ratios of the amounts of currents consumed at the individual power supply terminals based on layout information correlated with the amounts of source currents consumed, such as the areas of individual internal interconnection lines, the number of contacts that connect the individual internal interconnection lines to individual transistors, the areas of the contacts and the sum of the gate widths of the transistors to be connected to the individual internal interconnection lines, in addition to the widths of the individual power supply terminals. As a circuit block can be modeled by allocating current sources to the individual power supply terminals with the internal interconnection lines omitted, this method can simplify the net list.
The fourth method is to compress a net list in a circuit block leaving power supply terminals of the circuit block by using the Kirchhoff's law. One example of compressing a net list using the fourth method is disclosed in, for example, Japanese Unexamined Patent Publication No. Hei 5-47928. The publication discloses a voltage computing method for power supply lines, which computes voltages of bending points of power supply lines and connection points from layout data of an integrated circuit that has a hierarchical design and has child cells included in a parent cell. The method prepares resistor/current source networks from the layout data of the parent cell excluding the child cells and the child cells, converts the resistor/current source network of the child cells into an equivalent circuit network equivalent to the resistor/current source network and having fewer nodes, incorporates the equivalent circuit network of the child cells into the resistor/current source network of the parent cell excluding the child cells, acquires voltage values at individual nodes in the parent cell excluding the child cells by solving a simultaneous linear equation of the resistor/current source network having voltage sources set to nodes to be connected to external units, and acquires voltage values at individual nodes in the child cells by solving a simultaneous linear equation of the resistor/current source network having voltage sources set to nodes to be connected to outside the resistor/current source network of the child cells. As solutions are obtained separately for the child cells and the parent cell excluding the child cells, the order of the simultaneous linear equation becomes smaller, thus shortening the time needed to solve the simultaneous linear equation.
According to the first method, however, as a net list is prepared by converting basic elements, such as transistors, as circuit elements to current sources and replacing portions between nodes of the power supply lines to which the current sources are connected with resistor elements included in the power supply lines, the scale of the net list becomes larger in proportion to the number of basic elements, such as transistors. The practical processing limit for the basic elements is about several tens of thousands of transistors. In case where this method is adapted to a recent large-scale integrated circuit, the analysis takes a vast amount of time using the hardware resources of an ordinary computer and may not be possible due to insufficient hardware resources, such as memory, depending on the contents of the analysis. The method therefore has such a problem that analysis cannot be executed effectively within a practical time.
While the second method can perform analysis in a larger circuit scale than the first method, it has restrictions on practical computer hardware resources in terms of the time and resources with respect to LSIs having a scale of one million logic gates, such as the recent LSIs. In consideration of the future improvement on the circuit integration, the second method will have a difficulty in analyzing a power supply network.
According to the third method, layout information, such as the widths of individual power supply terminals in a circuit block which is simplified by omitting a part of a net list has a certain correlation with the values of source currents consumed in the individual power supply terminals. However, the values of consumed source currents are settled by the circuit design, have a correlation with layout in
Arent & Fox PLLC
Fujitsu Limited
Siek Vuthe
LandOfFree
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