Power supply method for semiconductor integrated circuit in...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000, C324S500000

Reexamination Certificate

active

07617463

ABSTRACT:
In a power supply port decision step, first, a required minimum number of power supply ports for use in a test is found based on power consumption information and the required minimum number of power bumps out of plural power bumps are decided as the power supply ports for use in the test. Then, processing is repeatedly performed until neither a voltage drop violation nor a current density violation is detected by a power mesh analysis. The processing consists of additionally deciding, as the power supply port for use in the test, a power bump corresponding to a place where the voltage drop violation occurs when the violation is detected by the power mesh analysis, and of modifying a layout of a place where the current density violation occurs when the violation is detected by the power mesh analysis.

REFERENCES:
patent: 6253354 (2001-06-01), Kuwano et al.
patent: 6584606 (2003-06-01), Chiu et al.
patent: 6868374 (2005-03-01), Ditlow et al.
patent: 6957413 (2005-10-01), McKeone et al.
patent: 2006/0095881 (2006-05-01), Kwon et al.
patent: 2006/0239102 (2006-10-01), Saita et al.
patent: 2004-234618 (2004-08-01), None
“Optimal placement of power-supply pads and pins” by Min Zhao, Yuhong Fu, Vladimir Zolotov, IEEE on Computer-aided design of integrated circuit and system, vol. 25, Jan. 2006.
“A Fast algorithm for power grid design”, by Jaskirat Singh and Sachin S. Sapatnekar, @ 2005 ACM.

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