Power-state management of peripheral device by north bridge...

Details Power-state management of peripheral device by north bridge... Power-state management of peripheral device by north bridge...

2005-08-04

2008-10-21

Patel, Nitin C (Department: 2116)

Electrical computers and digital processing systems: support

Computer power control

C713S320000, C713S323000

Reexamination Certificate

active

07441128

ABSTRACT:
In a power management method of a computer system, the CPU asserts a clock-suspending grant cycle in response to a clock-suspending signal issued by the south bridge chip, and the south bridge chip issues the clock-suspending signal in response to a data write cycle asserted by the CPU. The clock-suspending grant cycle is to be transmitted to the south bridge chip via the north bridge chip when the CPU is ready to enter a power-saving mode. The north bridge chip performs a first power management operation of the peripheral device in response to the clock-suspending grant cycle. The south bridge chip performs a second power management operation of the computer system in response to the clock-suspending grant cycle.

REFERENCES:
patent: 5892958 (1999-04-01), Nagashige et al.
patent: 6199134 (2001-03-01), Deschepper et al.
patent: 6360327 (2002-03-01), Hobson
patent: 6732280 (2004-05-01), Cheok et al.
patent: 2005/0039063 (2005-02-01), Hsu et al.

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