Power source design for embedded memory

Details Power source design for embedded memory Power source design for embedded memory

1998-11-23

1999-10-19

Nelms, David

Static information storage and retrieval

Powering

365 63, 365201, G11C 700

Patent

active

059700114

ABSTRACT:
A power source design for embedded memory uses independent power sources such that a first power source group is linked to the DRAM, a second power source group is linked to the logic unit and a third power source group is linked to the testing mode circuit with input/output ports during the silicon chip stage. In the packaging stage the first power source group, the second power source group and the third power source group are joined together. The design is able to prevent testing errors or instability due to direct current from floating nodes in the silicon chip testing stage, and prevent a potential latch-up problem in the packaging stage.

REFERENCES:
patent: 5287320 (1994-02-01), Adachi
patent: 5367487 (1994-11-01), Yoshida
patent: 5828826 (1998-10-01), Sato et al.
patent: 5889722 (1999-03-01), Numazaki et al.

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