Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices
Reexamination Certificate
2001-06-12
2002-10-15
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Making plural separate devices
C438S111000, C438S112000, C438S121000, C438S123000, C257S728000
Reexamination Certificate
active
06465276
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a power semiconductor package and a method for making the same, more particularly to a power semiconductor package with a power MOSFET die and a method for making the same.
2. Description of the Related Art
FIG. 1
illustrates a conventional power semiconductor package. The power semiconductor package includes a semiconductor die
11
, such as a power MOSFET die, which has a bottom surface defining a drain contact (not shown), and a top surface that includes a first metallized region defining a source contact
111
and a second metallized region defining a gate contact
112
. The power semiconductor package further includes a bottom metal plate
121
coupled to and electrically connected to the drain contact, a plurality of drain terminals
122
extending outwardly from the bottom metal plate
121
to be electrically connected to the drain contact, a plurality of spaced apart source terminals
123
electrically connected to the source contact
111
via a plurality of gold wires
125
, and a gate terminal
124
electrically connected to the gate contact
112
via a gold wire
126
.
The aforesaid power semiconductor package is disadvantageous in that in order to reduce the electrical resistance from the source contact
111
to the source terminals
123
, a large number of the gold wires
125
are required to be employed in the power semiconductor package. Since the gold wires
125
are very expensive and can only be stitch bonded to the source contact
111
and the source terminal
123
one at a time, such number of the gold wires
125
will increase the production cost and the manufacturing time considerably. In addition, the reduction of the electrical resistance is still poor, due to a relatively small increase in the cross-sectional area of the gold wires
125
when a large number of the gold wires
125
is employed. Moreover, the gold wires
125
may not be able to provide sufficient surface area for dissipating a large amount of heat generated by the semiconductor die
11
, particularly by a high current power MOSFET die, during operation.
FIG. 2
illustrates another conventional power semiconductor package that employs a metal plate
23
to replace the gold wires
125
so as to reduce the aforesaid electrical resistance and to increase the surface area as required to dissipate the aforementioned heat, and to reduce the manufacturing time due to elimination of the wire bonding operation for the gold wires
125
. However, the power semiconductor package of this type is disadvantageous in that two bonding apparatuses are needed for stitch bonding the gold wire
126
to the gate contact
112
and the gate terminal
124
and for bonding the metal plate
23
to the source contact
111
and the source terminals
123
in the production of the power semiconductor package. Moreover, the size of the metal plate
23
employed in the power semiconductor package is preferably as large as possible to cover the source contact
111
without extending to the gate contact
112
. However, the metal plate
23
is normally coupled to the source contact
111
via a conductive material, such as a conductive epoxy or a conductive paste, which can overflow and interfere with the surface of the gate contact
112
upon curing or reflowing of the conductive material. As a consequence, the gate contact
112
may be contaminated with the conductive material, and the gold wire
26
may be poorly stitch bonded to the gate contact
112
because of the aforesaid contamination.
SUMMARY OF THE INVENTION
Therefore, the object of the present invention is to provide a method for bonding a power semiconductor die to a lead frame via a metal sheet that is capable of overcoming the aforementioned problems.
Another object of the present invention is to provide a power semiconductor package that includes a power MOSFET die, a metal sheet coupled to a source contact on the power MOSFET die, and a terminal having a V-shaped end portion which is able to facilitate connection of the terminal to the metal sheet.
According to one aspect of the present invention, a method for bonding a power semiconductor die to a lead frame comprises the steps of: providing a power semiconductor die that has a bottom surface defining a drain contact, and a top surface which includes a first metallized region defining a source contact, and a second metallized region defining a gate contact; providing a lead frame that has first, second, and third terminals; providing a metal sheet that has first and second contacting portions and a bridging portion interconnecting the first and second contacting portions; mounting the power semiconductor die on the lead frame such that the drain contact is coupled to and is electrically connected to the first terminal; attaching the metal sheet to the top surface of the power semiconductor die and the second and third terminals of the lead frame such that the source contact and the second terminal are coupled to and are electrically connected to the first contacting portion, and such that the gate contact and the third terminal are coupled to and are electrically connected to the second contacting portion; and cutting the bridging portion for disconnecting electrically the first and second contacting portions.
According to another aspect of the present invention, a power semiconductor package comprises: a power MOSFET die that has a bottom surface defining a drain contact, and a top surface which includes a first metallized region defining a source contact, and a second metallized region defining a gate contact; a first metal sheet that is coupled to and that is electrically connected to the source contact, and that has one end extending outwardly from the power MOSFET die; a second metal sheet that is coupled to and that is electrically connected to the gate contact; a first terminal disposed adjacent to the power MOSFET die and coupled to and electrically connected to the drain contact; a second terminal disposed adjacent to the power MOSFET die and having a substantially V-shaped end portion that confines a substantially V-shaped groove to receive said one end of the first metal sheet, the V-shaped end portion of the second terminal being coupled to and being electrically connected to said one end of the first metal sheet; and a third terminal disposed adjacent to the power MOSFET die and coupled to and electrically connected to the second metal sheet.
REFERENCES:
patent: 5105536 (1992-04-01), Neugebauer et al.
patent: 5637922 (1997-06-01), Fillion et al.
patent: 6040626 (2000-03-01), Cheah et al.
patent: 6165820 (2000-12-01), Pace
patent: 6307755 (2001-10-01), Williams et al.
patent: 6319755 (2001-11-01), Mauri
Jr. Carl Whitehead
Knobbe Martens & Olson Bear LLP.
Siliconx (Taiwan) Ltd.
Vockrodt Jeff
LandOfFree
Power semiconductor package and method for making the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Power semiconductor package and method for making the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Power semiconductor package and method for making the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2952666