Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-06-28
2003-02-25
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S328000, C257S329000, C438S259000, C438S270000, C438S271000
Reexamination Certificate
active
06525373
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a power semiconductor device and a method for manufacturing the same, and more particularly, to a power semiconductor device having a trench-type gate and a method for manufacturing the same.
2. Description of the Related Art
Recently, as applied equipment becomes larger and has larger capacity, a power controlling semiconductor device having a high breakdown voltage, a high current capacity, and capable of high-speed switching is necessary. In such a power controlling semiconductor device, the power loss must be very small in a normal operation state. As a system becomes smaller, the power controlling semiconductor device also becomes smaller.
In the past, a double-diffused metal oxide semiconductor field effect transistor (DMOSFET) structure using a planar diffusion technology was generally used as the power controlling semiconductor device. Recently, a MOSFET structure of a trench gate type in which a trench is formed by etching a semiconductor substrate to a predetermined depth and the inside thereof is filled with a gate conductive layer, is sought.
In general, a semiconductor device having the trench type gate has more complicated manufacturing processes and requires one or two more masks than a semiconductor device having the planar structure. In the aspect of cost, it is more advantageous to increase the number of devices integrated in one chip, i.e., the number of net dies. However, since many processing steps and much processing time are required, it is uneconomical to increase the number of the net dies. Therefore, in the case of the MOSFET having the trench type gate or an insulated gate bipolar transistor (IGBT), it is necessary to reduce the number of masks.
FIG. 1
is a sectional view showing a power MOSFET of a conventional trench gate structure.
In
FIG. 1
, reference numerals
10
,
12
,
14
,
16
,
18
,
20
,
22
,
24
, and
26
respectively denote a semiconductor substrate
10
doped with high concentration of first conductive type impurities, an epitaxial layer
12
, a body region
14
doped with a low concentration of second conductive type impurities, a source region
16
, a gate insulating film
18
, a trench type gate
20
filled with polysilicon, an interlayer dielectric film
22
, a source electrode
24
connected to the source region, and a gate electrode
26
connected with the gate.
In a conventional technology, a gate is formed by forming a trench in a semiconductor substrate and completely filling the inside of the trench with polysilicon. The trench is formed to have a width of 1 &mgr;m in order to facilitate the filling. However, the contact margin must be not more than 0.25 &mgr;m in order to connect the gate formed in the trench to the gate electrode. Therefore, since a very precise processing level is required and the yield is lowered, it is uneconomical with respect to cost. Also, since the roughness of the surface of the polysilicon film filled in the trench is not uniform, it is difficult to stably form a contact to a gate electrode.
In order to solve such problems, in a conventional technology, the contact to a gate electrode
26
is facilitated by leaving the polysilicon film to have a certain thickness on the semiconductor substrate and patterning the polysilicon film using the mask as shown in FIG.
1
. However, according to this method, the number of masks increases, thus increasing manufacturing costs.
SUMMARY OF THE INVENTION
To solve the above problems, it is an objective of the present invention to provide a power semiconductor device by which it is possible to save manufacturing expenses by reducing the number of masks.
It is another objective of the present invention to provide a method of manufacturing the above power semiconductor device.
Accordingly, to achieve the first objective, a power semiconductor device of a trench gate structure according to the present invention includes a semiconductor substrate and a semiconductor region of a first conductive type formed on the semiconductor substrate. A source region of a second conductive type is formed on the semiconductor region. A trench is formed to pass through the source region and the semiconductor region of the first conductive layer. A first conductive layer, formed to be insulated from the semiconductor substrate by interposing a gate insulating film, and a gate formed of a second conductive layer surrounded by the first conductive layer are formed in the trench. An interlayer dielectric film is formed on the semiconductor substrate. A gate electrode is formed connected to the gate through a contact hole formed in the interlayer dielectric film. A source electrode is formed connected to the source region through a second contact hole formed in the interlayer dielectric film.
The width of the upper surface of the gate is preferably equal to or less than the width of the trench. The plane structure of the gate is circular or polygonal having at least five sides. In particular, the width of the trench in the part in which the gate contacts a gate electrode is preferably 2 &mgr;m.
The first conductive layer is formed of polysilicon and the second conductive layer is preferably formed of metal.
According to one embodiment, the semiconductor substrate comprises a first region highly doped with second conductive type impurities, and a second conductive region doped with the second conductive type impurities of low concentration.
According to another embodiment, the semiconductor substrate comprises a first region highly doped with first conductive type impurities, a second region highly doped with second conductive type impurities, and a third region formed on the first region and doped with the second conductive type impurities of low concentration.
To achieve the second object, in the method for manufacturing a power semiconductor device of a trench gate structure according to the present invention, a semiconductor region of a first conductive type is formed on a semiconductor substrate. A source region of a second conductive type is formed on the semiconductor region. A trench is formed in a predetermined region of the semiconductor substrate. A gate insulating film is formed on the semiconductor device in which the trench is formed. A gate formed of a first conductive layer, formed to be insulated from the semiconductor substrate by the gate insulating film, and a second conductive layer, surrounded by the first conductive layer, are formed in the trench. An interlayer dielectric film is formed on the semiconductor substrate in which the gate is formed. The source region and the gate are exposed by patterning the interlayer dielectric film. A source electrode and a gate electrode are formed respectively connected to the source region and the gate.
In the step of forming the trench on the semiconductor substrate, the width of the trench at the part where the gate contacts the gate electrode is formed to be about 2 &mgr;m. Also, the upper portion of the trench is formed to be circular or polygonal.
The step of forming the gate comprises the steps of sequentially depositing a first conductive layer and a second conductive layer on a semiconductor substrate on which a gate insulating film is formed and planarizing the surfaces of the second conductive layer and the first conductive layer thereby filling the second conductive layer and the first conductive layer in the trench.
The first conductive layer is formed of polysilicon and the second conductive layer is formed of metal.
According to one embodiment, the semiconductor substrate comprises a first region highly doped with second conductive type impurities and a second conductive region doped with the second conductive type impurities of low concentration.
According to another embodiment, the semiconductor substrate comprises a first region highly doped with the first conductive type impurities, a second region highly doped with the second conductive type impurities, and a third region formed on the first region and doped with the se
Fairchild Korea Semiconductor Ltd.
Kang Donghee
Loke Steven
Volentine & Francos, PLLC
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