Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
1999-01-26
2001-09-18
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C257S706000, C257S712000, C257S713000
Reexamination Certificate
active
06291893
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor devices, and, more particularly, to a semiconductor device and the connections thereto.
BACKGROUND OF THE INVENTION
As is known, an electronic semiconductor device, for example, an integrated circuit, is formed by a chip of semiconductor material which contains the active portions of the device. The integrated circuit also includes a structure for supporting the chip and for forming electrical interconnections thereby enabling the device to be connected to an external circuit.
Upon completion of its manufacture, the chip has a surface covered by a layer of insulating material. On the surface of the insulating material, metal interconnection elements appear in the form of pads which define the terminals of the electronic device.
An interconnection technique known as the “flip-chip” technique provides for a flat mounting substrate of insulating material on which there are metal tracks which terminate in areas arranged in a configuration mirroring that of the pads on the chip. A soldering material, for example, an alloy of lead and tin, is applied to the pads and, typically, takes the form of a hemispherical projection (a bump) on each pad. The chip is then placed on the mounting substrate with the pads mounted by the bumps in registry with the terminal areas of the metal tracks. The assembly is brought to the melting point of the soldering material so that the soldering material melts and, after cooling, solders the pads of the chip to the corresponding metal areas of the substrate. Finally, a thermosetting resin capsule is formed, incorporating the chip.
In comparison with another widely used interconnection technique which uses thin wires soldered at one end to the pads of the chip and at the other end to the metal terminals which form part of a terminal structure (a lead frame) which surrounds the chip, the “flip-chip” technique has various advantages. In particular, it enables contact pads to be arranged over the entire area of the chip and not only along the perimeter as is necessary with the other technique. The flip chip approach also permits very short interconnections and, finally, it takes up little space.
However, it may not be suitable for use in power applications in which the chip of semiconductor material is subject to a very high degree of heating. This is so since very little heat is dissipated from the chip to the substrate. The chip is joined to the substrate by only a few points with low thermal resistance which are the soldering points. Most of its surface is separated from the substrate by a space which is filled with the resin in which the chip is incorporated. Although the space is very shallow, the heat dissipation is limited by the relatively high thermal resistance of the resin.
To reduce the thermal resistance of the resin, it is known to include therein particles of material having lower thermal resistance. Even this measure does not greatly improve the performance of the device in power applications.
SUMMARY OF THE INVENTION
The object of the present invention is to propose a semiconductor device which can be connected by the “flip-chip” technique and which has good performance in power applications.
This object is achieved by a semiconductor device comprising a chip of semiconductor material, an electronic device formed at least partially in the chip and having a plurality of contact areas, and a layer of insulating material covering a major surface of the chip. A plurality of interconnection elements extends through the layer of insulating material from the contact areas to an opposite surface of the layer of insulating material defining substantially coplanar connection pads on the opposite surface. A plurality of solder elements are on the connection pads. The device also includes at least one metal plate extending on the layer of insulating material and having an extensive surface substantially coplanar with the connection pads. In addition, at least one soldering element is provided on the extensive surface of the at least one metal plate.
The metal plate is preferably partially incorporated into the layer of insulating material. The at least one metal plate may be in contact with a contact area of the electronic device. The at least one solder element on the extensive surface of the metal plate may comprise a plurality of solder elements, or a single continuous body of solder on the extensive surface of the metal plate. Of course, the electronic device may comprise a power component.
The invention is also directed to an integrated circuit assembly comprising the semiconductor device and a mounting substrate connected to the semiconductor device. More particularly, the mounting substrate preferably comprises a plurality of connection pads being connected to the connection pads of the semiconductor device, and at least one metal plate having an extensive surface connected to the extensive surface of the at least one metal plate of the semiconductor device.
A method aspect of the invention is for flip chip mounting of a semiconductor device on a mounting substrate. The method preferably comprises the steps of: providing at least one metal plate exposed on an insulating layer of the semiconductor device to be substantially coplanar with contact pads on the insulating layer; providing at least one metal plate exposed on the mounting substrate adjacent contact pads on the mounting substrate; and connecting the semiconductor device and the mounting substrate so that corresponding contact pads are connected together and so that corresponding metal plates are connected together.
REFERENCES:
patent: 5508230 (1996-04-01), Anderson et al.
patent: 5866942 (1999-02-01), Suzuki et al.
patent: 5977626 (1999-11-01), Wang et al.
patent: 0 600 590 (1994-06-01), None
patent: 0 637 078 (1995-02-01), None
Patent Abstracts of Japan, vol. 011, No. 376 (E-563), Dec. 8, 1987 & JP 62144346 A (Matsushita Electric Ind. Co. Ltd.).
Patent Abstracts of Japan, vol. 018, No. 299 (E-1558), Jun. 8, 1994 & JP 06 061304 A (NEC Corp.).
Crema Paolo
Mantovani Marco
Tiziani Roberto
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Brophy Jamie L.
Galanthay Theodore E.
Meier Stephen D.
STMicroelectronics S.r.l.
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